TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Data Sheet
June 2002
12 28-Channel Framer Registers (continued)
Table 447. FRM_HCR3, Transmit HDLC Channel Register 3 (R/W)
Address*
Bit
Name
Function
Reset
Default
0x8HP82
15
FRM_THC_RESET Transmit HDLC Reset. When this bit is 1, the channel is
0
held in reset.
This clears status for the channel, disables the channel,
and clears the FIFO for the channel.
14
FRM_TENABL
Transmit HDLC Enable. When this bit is 0, and written
to 1, the channel is reinitialized and enabled. When this bit
is 1, and written to 0, no further data will be transmitted
and any partial data being serialized will be lost. The
channel is disabled.
0
The user should reset the FIFO to prevent partial packets
from being transmitted once re-enabled. Writing the same
value as currently programmed has no effect.
13:11
RSVD
Reserved. Must write to 0.
000
00
Bits 10:0, 3, 1:0 can only be written as the channel is being enabled, (i.e., bit 14 held 0 and is now being
written to 1).
0x8HP82
10:9
FRM_CFLAGS[1:0] Closing Flags. Only valid in HDLC mode. These bits
select one of four values (00 = FRM_FCNT0[4:0],
01 = FRM_FCNT1[4:0], 10 = FRM_FCNT2[4:0],
11 = FRM_FCNT3[4:0] (Table 345—Table 348)). This
value indicates the number of additional closing flags
inserted after an HDLC packet (e.g., if FRM_FCNT2[4:0]
is selected and it is set to 00100, then five flags are
inserted).
8
7
FRM_PRMEN
PRM Enable. When 1, this channel is enabled to send
PRM packets automatically. When 0, this feature is dis-
abled. (Bit only for channels 1—28, or else reserved.)
0
0
When enabled, PRMs will not be sent until all four sec-
onds of PRM information are valid.
FRM_TLOOP
HDLC Controller Loopback. When this bit is set to 1, the
channel will operate in loopback mode. When 0, the chan-
nel operates normally.
Note: The corresponding Rx channel should be enabled
before enabling the Tx channel for loopback.
6
5
FRM_C_R
PRM C/R Bit. This bit is inserted as the C/R bit when
sending a PRM packet on this channel. (Bit only for chan-
nels 0—27, or else reserved.)
0
0
FRM_HTTHRSEL
Transmit Threshold Select. This bit selects which of the
two programmable FIFO threshold values to use for this
channel (0 selects FRM_HTTHRSH0, Table 339, 1
selects FRM_HTTHRSH1, Table 340).
4
FRM_IFCS
FCS Insert. Only valid in HDLC mode. When 0, this bit
indicates the FCS at the end of an HDLC packet should
be inserted. A 1 indicates that the internally computed
FCS will not be inserted at the end of the packet.
0
* See Table 444 on page 309 for mapping of H and P.
310
Agere Systems Inc.
ETC [ ETC ]
