TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Data Sheet
June 2002
12 28-Channel Framer Registers (continued)
12.20 28-Channel Framer Block Register Map
Table 459. Framer Register Map
Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.
Address
Symbol
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2 Bit 1
Bit 0
Superframer Global Registers—R/W
0x80000 FRM_SFGR1
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FRM_
SW_TRN
FRM_LC_CNTRL[1:0]
FRM_TP_
FRM_LOOP_ FRM_DS1_
FRM_PLL_
BYPAS
FRM_LG_BUF_MODE
TIMING
CEPTN
0x80001 FRM_SFGR2
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FRM_RP_
FRM_TP_
FRM_RP_
FRM_TP_ FRM_RP_ FRM_TS_
PWDN
FRM_RS_
PWDN
FRM_TP_ FRM_RP_ FRM_TP_
PM_PWDN FF_PWDN RA_PWDN
SIG_PWDN SIG_PWDN RDL_PWDN TDL_PWDN RH_PWDN TH_PWDN
0x80002 FRM_SFGR3
FRM_RP_ FRM_AR_IS
SIG
FRM_TP_
RDL_IS
FRM_TP_
TDL_IS
FRM_RH_IS FRM_TH_IS FRM_TS_ FRM_RS_ FRM_TP_
IS IS PM_IS
FRM_RP_ FRM_RP_ FRM_RP_
PM_IS RDL_IS TDL_IS
0
0
0
0
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(RO)
0x80003 FRM_SFGR4
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FRM_VERSION[2:0]
0x80004
—
RSVD
0x80009
Arbiter (Framer) Global Registers—R/W
0x80010
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FRM_FGR1
FRM_FGR2
FRM_FGR3
FM_DIS_
LHSCD
0x80011
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FRM_TC_
EN
FRM_TC[7:0]
0x80012
FRM_
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TPSSE_IM
0x80014
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FRM_FGR4
(COR)
FRM_TPSSEI[16:1]
0x80015
Page 250
FRM_FGR5
(COR)
FRM_TPSSEI[28:17]
316
Agere Systems Inc.
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