Data Sheet
June 2002
TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
Table 454. FRM_HCR10, Receive HDLC Channel Register 10 (R/W)
Address*
Bit
Name
Function
Reset
Default
0x8HP02
15
FRM_RHC_RESET Receive HDLC Reset. When this bit is 1, the channel is
0
held in reset.
14
13
RSVD
Reserved. Must write to 0.
0
0
FRM_RENABL
Receive HDLC Enable. When this bit is 0 and written to 1,
the channel is reinitialized (i.e., HDLC searching for open-
ing flag, transparent searching for alignment character if so
programmed) and enabled. When this bit is 1 and written to
0, any current HDLC packet will be aborted and the chan-
nel disabled. Writing the same value as currently pro-
grammed has no effect.
Reserved. Must write to 0.
12
RSVD
0
Bits 11:0 can only be written as the channel is being enabled (i.e., bit 13 held 0 and is now being
written to 1).
11
FRM_RTHRSEL Receive FIFO Threshold Select. This bit selects which of
the two programmable FIFO threshold values to use for
this channel. (0 selects FRM_HRTHRSH0[9:0]
0
(Table 353), 1 selects FRM_HRTHRSH1[9:0], Table 354).
10
FRM_RFCS
Receive FCS Option. Only valid in HDLC mode. When 1,
this bit indicates the FCS at the end of an HDLC packet
should be removed. A 0 indicates it should be kept as part
of the packet.
0
9
8
FRM_HRMODE
FRM_BYTAL
Receive Channel Mode Select. A 0 indicates the channel
is in HDLC mode. A 1 indicates the channel is in transpar-
ent mode.
0
0
Byte Alignment. This bit is only used in transparent mode
(forced to 1 in HDLC mode). A 0 indicates no byte align-
ment is done by the receiver. A 1 indicates that byte align-
ment will be done by the receiver once the
FRM_MATCH[7:0] code is found.
7:0
FRM_MATCH[7:0] Transparent Mode Pattern Match. Only valid in transpar-
ent mode with byte alignment. These bits indicate the pat-
tern to match to begin receiving transparent data (forced to
ones in HDLC mode).
0x0
* See Table 444 on page 309 for mapping of H and P.
Agere Systems Inc.
313
ETC [ ETC ]
