Data Sheet
June 2002
TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
Table 447. FRM_HCR3, Transmit HDLC Channel Register 3 (R/W) (continued)
Address*
Bit
Name
Function
Reset
Default
0x8HP82
3
FRM_HTIDLE
HDLC Idle Select. Only valid in HDLC mode. This bit indi-
cates the idle fill character when the Tx FIFO is empty. A 0
means fill with flags (01111110). A 1 means fill with idle
(11111111).
0
2
FRM_HTMODE
Transmit Channel Mode Select. A 0 indicates the chan-
nel is in HDLC mode. A 1 indicates the channel is in trans-
parent mode.
0
1:0
FRM_HXPIDLE[1:0] Transparent Idle Mode Character Select. Only valid in
transparent mode. These bits indicate one of the four pos-
00
sible 8-bit patterns to be sent when the Tx FIFO is empty.
(00 selects TXICHAR0, Table 341, 01 selects TXICHAR1,
Table 342, etc.)
* See Table 444 on page 309 for mapping of H and P.
Table 448. FRM_HCR4, Transmit HDLC Channel Register 4 (RO)
Address*
Bit
Name
Function
Reset
Default
Reserved. Reads 0.
0x8HP83
15:3
2
RSVD
0x000
0
FRM_HTUND
Transmit FIFO Underrun. A 1 indicates this channel has
run out of data in the middle of an HDLC packet. In trans-
parent mode, it simply means the channel has run out of
data.
1
0
FRM_HTDONE
Transmit Done. A 1 indicates a complete packet has been
sent on this channel.
0
0
FRM_HTTHRSH Transmit FIFO Threshold Interrupt. A 1 indicates this
channel’s FIFO level has dropped below the programmed
threshold value.
* See Table 444 on page 309 for mapping of H and P.
Table 449. FRM_HCR5, Transmit HDLC Channel Register 5 (R/W)
Address*
Bit
Name
Function
Reset
Default
Reserved. Must write to 0.
0x8HP84
15:3
2
RSVD
0x0
0
FRM_MHTUND
Transmit FIFO Underrun Interrupt Mask. A 1 masks the
corresponding channel’s FRM_HTUND status from caus-
ing an interrupt.
1
0
FRM_MHTDONE Transmit Done Interrupt Mask. A 1 masks the corre-
sponding channel’s FRM_HTDONE status from causing
an interrupt.
0
0
FRM_MHTTHRSH Transmit FIFO Threshold Interrupt Mask. A 1 masks the
corresponding channel’s FRM_HTTHRSH status from
causing an interrupt.
* See Table 444 on page 309 for mapping of H and P.
Agere Systems Inc.
311
ETC [ ETC ]
