Data Sheet
June 2002
TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
12.19 HDLC Per Channel Configuration and Status Registers
Table 444. HDLC Per Channel Register Addressing Map
Address Pins (ADDR15—ADDR0)
15 14
13
HDLC Channels 1—64 (000000—111111) RXP= 0/
TXP = 1
12
11
10
9
8
7
6
0
5
0
4
0
3
2
1
0
0
1
Per Channel Register
HDL9 HDL8 HDL7 HDL6 HDL5 HDL4
H* P*
HDL3 HDL2 HDL1 HDL0
—
* H and P represent hexidecimal digits used for absolute addressing in Table 445 through Table 458.
Table 445. FRM_HCR1, Transmit HDLC Channel Register 1 (R/W)
Address*
Bit
Name
Function
Reset
Default
Reserved. Must write to 0.
0x8HP80 15:13
RSVD
000
0x0
12:8 FRM_TTIMESLOT[4:0] Transmit HDLC Time Slot.
These bits indicate (in binary) the time-slot number
assigned to this channel.
7:0
FRM_TBIT_IM[7:0]
Transmit HDLC Bit Assignment.
0x00
These bits indicate which bits of a time slot are to be
assigned to this channel (1 = bit assigned).
In loopback mode, set as follows:
00000000 = slowest (~6 kbits/s at 52 MHz).
10000000 = faster (~2x above).
11000000 = faster still (~4x slowest rate).
. . . .
11111111 = fastest (~1.5 Mbits/s at 52 MHz).
Note: If running a mix of loopback and nonloopback
channels, the loopback speed should not be set
faster than 11100000.
* See Table 444 for mapping of H and P.
Table 446. FRM_HCR2, Transmit HDLC Channel Register 2 (R/W)
Address* Bit Name
Function
Reset
Default
0x8HP81 15:14 FRM_TFRAME_SEL[1:0] Transmit HDLC Frame Select.
These bits are encoded to select odd and/or even num-
00
bered frames assigned to this channel.
00 = no data selected.
01 = data to even frames selected (FS, FAS).
10 = data to odd frames selected (FT, NOTFAS, ESF-DL).
11 = data to all (even and odd) frames selected.
13:5
4:0
RSVD
Reserved. Must write to 0.
0x000
00000
FRM_TLINK[4:0]
Transmit HDLC Link Select.
These bits indicate (in binary) the link number assigned to
this channel.
* See Table 444 for mapping of H and P.
Agere Systems Inc.
309
ETC [ ETC ]
