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TMXF281553BAL-3C-DB 参数 Datasheet PDF下载

TMXF281553BAL-3C-DB图片预览
型号: TMXF281553BAL-3C-DB
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内容描述: 电信/数据通信\n [Telecomm/Datacomm ]
分类和应用: 电信数据通信
文件页数/大小: 784 页 / 10078 K
品牌: ETC [ ETC ]
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Data Sheet  
June 2002  
TMXF28155 Supermapper  
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1  
12 28-Channel Framer Registers (continued)  
Table 425. FRM_TFDLLR7, Transmit FDL Link Register 7 (R/W)  
Address* Bit  
Name  
Function  
Reset  
Default  
0x8LTD6 15:7  
6
RSVD  
Reserved. Must write to 0.  
0x000  
0
FRM_BOME  
Transmit Bit-Oriented Message Enable. A 1 indicates that the  
BOM message register has been initialized and should be transmit-  
ted on the data link of the ESF frame. The pattern will continue to  
be transmitted until the enable is removed. When set to 0, the BOM  
transmission will stop immediately without completing the current  
pattern transmission or without completing the series of 10 pat-  
terns.  
5:0 FRM_TBOM[5:0] Transmit Bit-Oriented Message. Indicates the contents of the  
BOM to be transmitted when enabled with FRM_BOME. A pattern  
of 111110 implies a BOM of 0111110011111111 with the  
0
right-most bit being transmitted first.  
* See Table 422 on page 295 for values of L and T.  
Table 426. FRM_TFDLLR8, Transmit FDL Link Register 8 (RO/COW)  
Address* Bit  
0x8LTD7 15:2  
1
Name  
Function  
Reset  
Default  
RSVD  
Reserved. Must write to 0.  
0000000  
0000000  
FRM_BOMC_IS BOM Complete Interrupt. (Clear on write.) A 1 indicates that  
the BOM register contents have been transmitted 10 times over  
the data link of the ESF frame.  
0
0
FRM_TXSE_IS Tx Stack Empty Interrupt. (Clear on write.) A 1 indicates that  
the Tx stack is empty. 0 indicates that the host has finished  
updating the stack. The Tx data link block sets this bit when the  
stack is empty, and needs to be filled if the D bits or Sa bits  
require changing. If the stack is not refilled, the old data will be  
retransmitted.The new data can be written anytime without  
interfering with the current transmission. The stack needs to be  
updated within 9 ms for an SLC-96 link or 4 ms for a CEPT link  
in order for the new information to be transmitted in the next  
double multiframe.  
1
* See Table 422 on page 295 for values of L and T.  
Table 427. FRM_TFDLLR9, Transmit FDL Link Register 9 (R/W)  
Address* Bit  
Name  
Function  
Reset  
Default  
0x8LTD8 15:2  
RSVD  
Reserved. Must write to 0.  
0000000  
0000000  
1
0
FRM_BOMC_IM Mask BOM Complete Interrupt. A 1 masks the BOM complete  
1
interrupt, FRM_BOMC.  
FRM_TXSE_IM Mask Tx Stack Empty Interrupt. A 1 masks the Tx stack  
1
empty interrupt, FRM_TXSE.  
* See Table 422 on page 295 for values of L and T.  
Agere Systems Inc.  
297  
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