TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Data Sheet
June 2002
12 28-Channel Framer Registers (continued)
Table 424. FRM_TFDLLR6, Transmit FDL Link Register 6 (R/W)
Address* Bit
Name
Function
Reset
Default
Reserved. Must write to 0.
0x8LTD5 15:8
7
RSVD
0x0
FRM_SA8SC
Sa8 Source Control. A 1 indicates that Sa8 is sourced from the
TXFDL stack. Zero indicates that Sa8 is sourced from the time
slot 0 data of the system interface in switching mode, or from
time slot 0 data received by the transmit path receive aligner in
transparent mode.
0
0
0
0
0
6
5
4
3
FRM_SA7SC
FRM_SA6SC
FRM_SA5SC
FRM_SA4SC
Sa7 Source Control. A 1 indicates that Sa7 is sourced from the
TXFDL stack. Zero indicates that Sa7 is sourced from the time
slot 0 data of the system interface in switching mode, or from
time slot 0 data received by the transmit path receive aligner in
transparent mode.
Sa6 Source Control. A 1 indicates that Sa6 is sourced from the
TXFDL stack. Zero indicates that Sa6 is sourced from the time
slot 0 data of the system interface in switching mode, or from
time slot 0 data received by the transmit path receive aligner in
transparent mode.
Sa5 Source Control. A 1 indicates that Sa5 is sourced from the
TXFDL stack. Zero indicates that Sa5 is sourced from the time
slot 0 data of the system interface in switching mode, or from
time slot 0 data received by the transmit path receive aligner in
transparent mode.
Sa4 Source Control. A 1 indicates that Sa4 is sourced from the
TXFDL stack. Zero indicates that Sa4 is sourced from the time
slot 0 data of the system interface in switching mode, or from
time slot 0 data received by the transmit path receive aligner in
transparent mode.
2
1
0
FRM_TXCRCSM CEPT CRC-4 Stack Mode. When set to 0, the Sa bits will be
transmitted based on being active. If MFA is lost, the stack will
not be transmitted. When set to 1, the Sa bits will be transmitted
based on BFA (basic frame alignment) only.
0
0
0
FRM_ASRC
Alignment Source. A 1 indicates that the MFA and BFA will be
used to determine if a BOM or stack is transmitted. A 0 indicates
that, when enabled for insertion, BOMs and stacks will be
inserted whenever the TDM data is requested.
FRM_DS1I
DS1 Insertion. A 1 enables this block to insert the contents of
the stack into the associated DS1 link. For SLC-96 links, D bits
will be inserted given the associated stack format. For DDS
links, data-link bits will be inserted given the associated stack
format. For other DS1 link types, this bit has no effect. A 0 dis-
ables this block from inserting D bits or data link bits into the
associated link.
* See Table 422 on page 295 for values of L and T.
296
Agere Systems Inc.
ETC [ ETC ]
