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TMXF281553BAL-3C-DB 参数 Datasheet PDF下载

TMXF281553BAL-3C-DB图片预览
型号: TMXF281553BAL-3C-DB
PDF下载: 下载PDF文件 查看货源
内容描述: 电信/数据通信\n [Telecomm/Datacomm ]
分类和应用: 电信数据通信
文件页数/大小: 784 页 / 10078 K
品牌: ETC [ ETC ]
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TMXF28155 Supermapper  
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1  
Data Sheet  
June 2002  
12 28-Channel Framer Registers (continued)  
Table 415. Receive Path Facility Data Link Registers Address Indexing  
Read: for link 1, the hexidecimal digit L is 0x0 and the hexidecimal digit R is 0x2.  
Link  
1
L
R
Link  
8
L
R
Link  
16  
17  
18  
19  
20  
21  
22  
23  
L
R
Link  
24  
25  
26  
27  
28  
L
R
0x0  
0x0  
0x0  
0x0  
0x0  
0x0  
0x0  
0x2  
0x4  
0x6  
0x8  
0xA  
0xC  
0xE  
0x1  
0x1  
0x1  
0x1  
0x1  
0x1  
0x1  
0x1  
0x0  
0x2  
0x4  
0x6  
0x8  
0xA  
0xC  
0xE  
0x2  
0x2  
0x2  
0x2  
0x2  
0x2  
0x2  
0x2  
0x0  
0x2  
0x4  
0x6  
0x8  
0xA  
0xC  
0xE  
0x3  
0x3  
0x3  
0x3  
0x3  
0x0  
0x2  
0x4  
0x6  
0x8  
2
9
3
10  
11  
12  
13  
14  
15  
4
5
6
7
Table 416. FRM_RFDLLR1—FRM_RFDLLR5, Receive FDL Link Registers 1—5 (RO)  
Address*  
Bit  
Name  
Function  
Reset  
Default  
Rx Stack Data 0.  
Rx Stack Data 1.  
Rx Stack Data 2.  
Rx Stack Data 3.  
Rx Stack Data 4.  
0x8LRC0  
0x8LRC1  
0x8LRC2  
0x8LRC3  
0x8LRC4  
15:0  
15:0  
15:0  
15:0  
15:0  
FRM_RXS0[15:0]  
FRM_RXS1[15:0]  
FRM_RXS2[15:0]  
FRM_RXS3[15:0]  
FRM_RXS4[15:0]  
0x0  
0x0  
0x0  
0x0  
0x0  
* See Table 415 for values of L and R.  
Table 417. FRM_RFDLLR6, Receive FDL Link Register 6 (R/W)  
Address*  
Bit  
Name  
Function  
Reset  
Default  
Reserved. Must write to 0.  
0x8LRC5  
15:1  
0
RSVD  
0x0  
0
FRM_RXCRCSM CEPT CRC-4 Stack Mode. When set to 0, the Sa bits will  
be stored based on multiframe alignment. If multiframe  
alignment is lost, the stack will not be made available to the  
host. When set to 1, the Sa bits will be stored based on an  
arbitrary multiframe alignment when only basic frame  
alignment can be established.  
* See Table 415 for values of L and R.  
Table 418. FRM_RFDLLR7, Receive FDL Link Register 7 (RO)  
Address*  
Bit  
Name  
Function  
Reset  
Default  
0x8LRC6  
15:1  
0
RSVD  
Reserved. Reads 0.  
0x0  
0
FRM_RXSA Rx Stack Available. A 1 indicates that the Rx stack is available  
for reading. 0 indicates that the stack is being updated and  
should not be read. In order to prevent a mix of old and new  
data being read, the host should verify that this bit is set to 1  
before continuing to read the stack.  
* See Table 415 for values of L and R.  
294  
Agere Systems Inc.  
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