Data Sheet
June 2002
TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
Table 412. FRM_PMLR19, Performance Monitor Link Register 19 (COR)
This register applies to the receive path only.
Address* Bit
Name
Function
Reset
Default
0x8LP92 15:5
RSVD
Reserved. Must write to 0.
0x000
0000
4:1 FRM_HGALIGN[3:0] Indicates HG Alignment for the Associated HG on Each
Link. The status will be given for a particular link any time
that link appears on the TDM bus. A 1 in any bit position indi-
cates that alignment has been achieved. A 0 indicates align-
ment is lost or handling groups are disabled.
Note: For receive path only.
0
FRM_SEFS
Severely Errored Frame Status. (See ANSI T1.403
0
9.4.2.2.2 for ESF and T1.231 6.1.2.2.2 for SF.)
Note: For receive and transmit path.
* See Table 393 on page 279 for values of L and P.
Table 413. FRM_PMLR20, Performance Monitor Link Register 20 (COR)
Address*
Bit
Name
Function
Reset
Default
0x8LP93
15:13
RSVD
Reserved. Must write to 0.
000
0
12:7
6
FRM_G[6:1] PRM Message Bit G6—G1.
FRM_SE
FRM_FE
FRM_LV
FRM_SL
FRM_LB
FRM_N1
FRM_N0
PRM Message Bit SE.
PRM Message Bit FE.
PRM Message Bit LV.
PRM Message Bit SL.
PRM Message Bit LB.
PRM Message Bit N1.
PRM Message Bit N0.
0
5
0
4
0
3
0
2
0
1
0
0
0
* See Table 393 on page 279 for values of L and P.
12.11 Receive Facility Data Link Configuration and Status Registers
Table 414. Receive Facility Data Link Register Addressing Map
Address Pins (ADDR15—ADDR0)
15 14
13
LNK4 LNK3 LNK2 LNK1 LNK0
L* R*
12
11
10
9
8
7
1
6
1
5
0
4
0
3
2
1
0
0
0
RXP = 0
RDL3 RDL2 RDL1 RDL0
—
* L and R represent hexidecimal digits used for absolute addressing in Table 416 on page 294 through Table 420 on page 295.
Agere Systems Inc.
293
ETC [ ETC ]
