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TMXF281553BAL-3C-DB 参数 Datasheet PDF下载

TMXF281553BAL-3C-DB图片预览
型号: TMXF281553BAL-3C-DB
PDF下载: 下载PDF文件 查看货源
内容描述: 电信/数据通信\n [Telecomm/Datacomm ]
分类和应用: 电信数据通信
文件页数/大小: 784 页 / 10078 K
品牌: ETC [ ETC ]
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Data Sheet  
June 2002  
TMXF28155 Supermapper  
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1  
12 28-Channel Framer Registers (continued)  
Table 419. FRM_RFDLLR8, Receive FDL Link Register 8 (COR)  
Address*  
Bit  
Name  
Function  
Reset  
Default  
0x8LRC7 15:1  
0
RSVD  
Reserved. Reads 0.  
0x0  
0
FRM_RXSR_IS Rx Stack Ready Interrupt. A 1 indicates that the Rx stack has  
been filled with data following the format of the associated link.  
* See Table 415 on page 294 for values of L and R.  
Table 420. FRM_RFDLLR9, Receive FDL Link Register 9 (R/W)  
Address*  
Bit  
Name  
Function  
Reset  
Default  
0x8LRC8  
15:1  
0
RSVD  
Reserved. Must write to 0.  
0x0  
1
FRM_MRXSR Mask Rx Stack Ready Interrupt. A 1 masks the Rx stack  
ready interrupt.  
* See Table 415 on page 294 for values of L and R.  
12.12 Transmit Facility Data Link Configuration and Status Registers  
Table 421. Transmit Facility Data Link Register Addressing Map  
Address Pins (ADDR15—ADDR0)  
15 14  
13  
LNK4 LNK3 LNK2 LNK1 LNK0  
L* T*  
12  
11  
10  
9
8
7
1
6
1
5
0
4
1
3
2
1
0
0
0
TXP = 1  
TDL3 TDL2 TDL1 TDL0  
* L and R represent hexidecimal digits used for absolute addressing in Table 423 through Table 427.  
Table 422. Transmit Path Facility Data Link Registers Address Indexing  
Read: for link 1, the hexidecimal digit L is 0x0 and the hexidecimal digit T is 0x3.  
Link  
1
L
T
Link  
8
L
T
Link  
16  
17  
18  
19  
20  
21  
22  
23  
L
T
Link  
24  
25  
26  
27  
28  
L
T
0x0  
0x0  
0x0  
0x0  
0x0  
0x0  
0x0  
0x3  
0x5  
0x7  
0x9  
0xB  
0xD  
0xF  
0x1  
0x1  
0x1  
0x1  
0x1  
0x1  
0x1  
0x1  
0x1  
0x3  
0x5  
0x7  
0x9  
0xB  
0xD  
0xF  
0x2  
0x2  
0x2  
0x2  
0x2  
0x2  
0x2  
0x2  
0x1  
0x3  
0x5  
0x7  
0x9  
0xB  
0xD  
0xF  
0x3  
0x3  
0x3  
0x3  
0x3  
0x1  
0x3  
0x5  
0x7  
0x9  
2
9
3
10  
11  
12  
13  
14  
15  
4
5
6
7
Table 423. FRM_TFDLLR1—FRM_TFDLR5, Transmit FDL Link Registers 1—5 (COR)  
Address*  
0x8LTD0  
0x8LTD1  
0x8LTD2  
0x8LTD3  
0x8LTD4  
Bit  
Name  
Function  
Reset Default  
0x0000  
Tx Stack Data 0.  
Tx Stack Data 1.  
Tx Stack Data 2.  
Tx Stack Data 3.  
Tx Stack Data 4.  
15:0  
15:0  
15:0  
15:0  
15:0  
FRM_TXS0[15:0]  
FRM_TXS1[15:0]  
FRM_TXS2[15:0]  
FRM_TXS3[15:0]  
FRM_TXS4[15:0]  
0x0000  
0x0000  
0x0000  
0x0000  
* See Table 422 for values of L and T.  
Agere Systems Inc.  
295  
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