TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Data Sheet
June 2002
12 28-Channel Framer Registers (continued)
12.15 Arbiter Framer Per Link Registers
Table 433. FRM_ARLR1, Arbiter Link Register 1 (R/W)
Address*
Bit
Name
Function
Reset
Default
0x8LPF0
15
FRM_LNK_ENA
Link Enable.
1
0 = link is disabled.
1 = link is enabled.
14
FRM_LNK_TRANSP
Transparent Mode Selection.
0
Switching:
0 = the link is in a nontransparent mode. (Regenerate
framing bits and CRC bits.)
1 = the link is in transparent mode. (Flow through framing
bits and CRC bits.)
Transport:
0 = nontransparent mode (regenerate CRC bits and flow
through framing bits).
1 = transparent mode (flow through framing bits and CRC
bits).
13
12
FRM_LNK_RESTARTN Restart Link.
0 = Restart the link.
1 = Normal operational mode for the link.
FRM_LNK_REFRAME Force Reframe.
0
0
0 = normal operational mode for the link.
1 = link is forced to reframe.
Reserved. Must write to 0.
Input Clock Edge Selection.
11:10
9
RSVD
0
0
FRM_ICKEDGE
0 = sample data on rising edge of input clock.
1 = sample data on falling edge of input clock.
8:0
RSVD
Reserved. Must write to 0.
000
* See Table 429 on page 298 for values of L and P.
300
Agere Systems Inc.
ETC [ ETC ]
