iW1688
Low-Power Off-line Digital PWM Controller
Calculate CBULK(MIN) and VBULK(MIN)
2
2
VBULK(MIN) ×TON
LM =
(10.4)
2PIN ×TP ×1.3
(
)
In typical applications, the bulk capacitor is chosen so that
the bulk capacitor voltage drops to 70% of the VINDC peak
before the next charging cycle. (If a longer holdup time is
needed then a larger bulk capacitor should be used)
With a known primary inductance of the transformer the
primary peak current will be:
VBULK(MIN) = 0.7×125V = 87.5V
VBULK(MAX ) = VINDC(MAX ) = 372V
VBULK(MIN) ×TON
(10.5)
IPRPK =
LM
(10.1)
PIN
2
CBULK =
From equation (10.4) since all factors are known and
TON(MAX) = 11.3 μs, the primary inductance will be:
2
fIN × VINDC(MIN) −VBULK(MIN)
(
)
2
932 × 11.3×10−6
PIN
(
)
2
VBULK(MIN) = VINDC(MIN) −
(10.2)
LM =
LM =
2×5.7× 25×10−6 ×1.3
fIN × CBULK
(
)
3.87mH
1.3
With 4 W output and 70% of efficiency power in (PIN) will
be:
LM = 2.96mH
POUT
(10.3)
PIN =
η
From equation (10.5)
93×11.3×10−6
2.96×10−3
4W
IPRPK =
PIN =
= 5.7W
70%
IPRPK = 355mA
Substitute value of Pin,VBULK(MIN) and VBULK(MAX) into equation
(10.1). Solving for CBULK
:
Calculating the turns ratio:
5.7
In Discontinuous Conduction Mode (DCM)
TP = TON + TRESET + TDEAD
CBULK =
=12µF
1252 − 87.52 × 60
(
)
(10.6)
CBULK = 6.8µF × 2 =13.6µF
To ensure the circuit remains in DCM a dead time (TDEAD
)
is established so that the maximum TON plus TRESET is about
85% of full period (TP or TDEAD is 15% of TP). If TDEAD is more
than 15% of TP then lower efficiency can be expected. If
TDEAD is less than 15% then the iW1688 may go into CC
mode.
Since we know CBULK then from equation (10.2):
5.7
VBULK(MIN) = 1252 −
60×13.6×10−6
VBULK(MIN) = 93V
TRESET = 85%TP −TON
(10.7)
Calculating primary inductance and peak current:
VIN × TON = NVOUT ×TRESET
The maximum TON is 10.3 μs at a minimum voltage of 93 V.
The transformer should be designed to meet these operating
conditions. The primary inductance will be:
Or:
VIN × TON
(10.8)
N =
VOUT × TRESET
2
2
VBULK(MIN) ×TON
LM =
2PIN ×TP
In the worst case of 90VAC input and full load output, then
from (10.7)
To minimize the output ripple and noise due to the transition
between (CV) and (CC) mode or vise versa, we set the CC
limit up to 130% of the maximum output power, or
TRESET = 85%× 25µs −11.3µs
TRESET = 9.95µs
MK-4AA003-E
03/16/06
PAGE 10
PRELIMINARY
ETC [ ETC ]
