Data Sheet
June 1999
ORCA Series 2 FPGAs
Timing Characteristics (continued)
Table 45B. OR2TxxB Global Input to Clock Setup/Hold Time (Pin-to-Pin)
OR2TxxB Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C.
Speed
Description
(TJ = all, VDD = all)
Device
-7
-8
Unit
Min
0.0
0.0
4.7
7.7
Max
—
—
—
—
Min
0.0
0.0
4.0
5.5
Max
—
—
—
—
Input to CLK (TTL/CMOS)
Setup Time (no delay)
Input to CLK (TTL/CMOS)
Setup Time (delayed)
OR2T15B
OR2T40B
OR2T15B
OR2T40B
ns
ns
ns
ns
ns
ns
Input to CLK (TTL/CMOS)
Hold Time (no delay)
OR2T15B
OR2T40B
1.6
1.4
0.0
0.0
—
—
—
—
1.4
1.3
0.0
0.0
—
—
—
—
Input to CLK (TTL/CMOS)
Hold Time (delayed)
OR2T15B
OR2T40B
ns
ns
Notes:
The pin-to-pin timing parameters in this table should be used instead of results reported by ORCA Foundry.
This clock delay is for a fully routed clock tree that uses the primary clock network. It includes both the input buffer delay and the clock routing to
the PFU CLK input. The delay will be reduced if any of the clock branches are not used. The given Setup (delayed and no delay) and Hold
(delayed) timing allows the input clock pin to be located in any PIC on any side of the device, but direct I/O→FF routing must be used. The Hold
(no delay) timing assumes the clock pin is located at one of the four center PICs and direct I/O→FF routing is used. If it is not located at one of
the four center PICs, this delay must be increased by up to the following amounts: OR2T15B = 5.7%, OR2T40B = 12.5%.
INPUT
CLK
D
Q
5-4847(F)
Figure 64. Global Input to Clock Setup/Hold Time
Lucent Technologies Inc.
155
ETC [ ETC ]
