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L3M
TXC-03452B
DATA SHEET
Figure 28. Motorola Microprocessor Write Cycle Timing
tH(1)
A(7-0)
D(7-0)
tH(2)
tSU(2)
tSU(4)
SEL
tPW(1)
tSU(1)
tH(3)
tSU(3)
RD/WR
tPW(2)
tF
DTACK
tD
Parameter
Symbol
Min
Typ
Max
Unit
A(7-0) address hold time after SEL↑
A(7-0) address valid set-up time to SEL↓
D(7-0) data valid set-up time to SEL↑
D(7-0) data hold time after SEL↑
SEL pulse width
tH(1)
tSU(1)
tSU(2)
tH(2)
tPW(1)
tSU(3)
tH(3)
tD
3.0
10.0
8.0
ns
ns
ns
ns
ns
ns
ns
ns
6.0
40.0
5.0
RD/WR↓ set-up time to SEL↓
RD/WR↓ hold time after SEL↑
DTACK↑ delay after SEL↓
3.0
15.0
DTACK pulse width
tPW(2)
tF
0.0
48 * Rcyc
10.0
ns
ns
ns
DTACK float time after SEL↑
RAM cycle D(7-0) valid set-up time to
tSU(4)
-2 * Rcyc
SEL↓
Note:
Rcyc is the period, in nanoseconds, of the RAM clock (RAMCI)
(e.g., RAMCI @ 25MHz yields: tSU(4)=-80ns min, tPW(2) = 1.92µs max).
TXC-03452B-MB
Ed. 6, April 2001
- 47 of 96 -
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