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L3M
TXC-03452B
DATA SHEET
Figure 26. Intel Microprocessor Write Cycle Timing
tH(1)
A(7-0)
D(7-0)
tH(2)
tSU(2)
tSU(1)
tSU(4)
SEL
WR
tSU(3)
tPW(1)
tF
tD(1)
tD(2)
RDY
tPW(2)
Parameter
Symbol
Min
Typ
Max
Unit
A(7-0) address hold time after WR↑
A(7-0) address set-up time to SEL↓
D(7-0) data valid set-up time to WR↑
D(7-0) data hold time after WR↑
SEL↓ set-up time to WR↓
tH(1)
tSU(1)
tSU(2)
tH(2)
3.0
0.0
ns
ns
ns
ns
ns
ns
ns
ns
8.0
6.0
tSU(3)
tPW(1)
tD(1)
10.0
40.0
WR pulse width
RDY↑ delay after SEL↓
10.0
16.0
RDY↓ delay after WR↓
tD(2)
RDY pulse width *
tPW(2)
tF
0.0
48 * Rcyc
10.0
ns
ns
ns
RDY float time after SEL↑
RAM cycle D(7-0) valid set-up time to WR↓
tSU(4)
-2 * Rcyc
* Note: RDY goes low when the address being written to corresponds to a RAM location but remains high dur-
ing status or control register access.
Rcyc is the period, in nanoseconds, of the RAM clock (RAMCI) (e.g., RAMCI @ 25MHz yields:
tSU(4)=-80ns min, tPW(2) = 1.92µs max)
TXC-03452B-MB
Ed. 6, April 2001
- 45 of 96 -
ETC [ ETC ]
