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L3M
TXC-03452B
DATA SHEET
Figure 27. Motorola Microprocessor Read Cycle Timing
tH(1)
A(7-0)
D(7-0)
tSU(1)
tF(1)
tPW(1)
SEL
tH(3)
tSU(2)
RD/WR
tD(1)
tF(2)
tPW(2)
DTACK
tD(2)
Parameter
Symbol
Min
Typ
Max
Unit
A(7-0) address hold time after SEL↑
A(7-0) address valid set-up time to SEL↓
D(7-0) data valid delay after DTACK↓
D(7-0) data float time after SEL↑
SEL pulse width
tH(1)
tSU(1)
tD(1)
3.0
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
10.0
5.0
6.0
tF(1)
tPW(1)
tSU(2)
tH(3)
40.0
5.0
RD/WR↑ set-up time to SEL↓
RD/WR↑ hold time after SEL↑
DTACK↑ delay after SEL↓
3.0
tD(2)
16.0
DTACK pulse width
tPW(2)
tF(2)
0.0
48 * Rcyc
10.0
DTACK float time after SEL↑
Note:
Rcyc is the period, in nanoseconds, of the RAM clock (RAMCI)
(e.g., RAMCI @ 25 MHz yields tPW(2) = 1.92µs max).
TXC-03452B-MB
Ed. 6, April 2001
- 46 of 96 -
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