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L3M
TXC-03452B
DATA SHEET
Figure 13. STS-3 Drop Bus Interface Timing
tCYC
tPWH
DCLK
(INPUT)
tH
tSU
DDATA(7-0)
DPAR
(INPUTS)
J1
STS-1 #1
SPE
STS-1 #2
DATA
STS-1 #1
SPE
STS-1 #3
C1(1)
C1(2)
C1(3)
DSPE
(INPUT)
tSU
tH
J1 for
STS-1#1
DC1J1
(INPUT)
C1(1)
Note: The relationship between J1 and the SPE signals is shown for illustration purposes
only, and will be a function of the pointer offset. For the STS-3 format, there will be
three J1 pulses which indicate the start of each of the STS-1 SPEs. The C1 pulse
is shown dotted because the C1 pulse may be provided on the DC1 signal lead. If
the DC1 signal lead is not used, it must be grounded.
Parameter
DCLK clock period
Symbol
Min
Typ
Max
Unit
tCYC
--
51.44
50
ns
%
DCLK duty cycle, tPWH/tCYC
40
60
DDATA(7-0) data/DPAR/DC1J1 set-up
tSU
7.0
ns
time to DCLK↓
DDATA(7-0) data/DPAR/DC1J1 hold time
tH
3.0
ns
after DCLK↓
TXC-03452B-MB
Ed. 6, April 2001
- 33 of 96 -
ETC [ ETC ]
