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L3M
TXC-03452B
DATA SHEET
Figure 15. STS-1 Add Bus Interface Timing Using an External Clock
tH
min = 3 ns
tSU
min = 7 ns
tOD min = 7 ns
max = 25 ns
XC1
(INPUT)
tCYC(1)
tPWH(1)
XCLKI
(INPUT)
tOD(3)
tCYC(2)
tPWH(2)
ACLK
(OUTPUT)
tOD(1)
tOD(1)
ASPE
(OUTPUT)
AC1J1
(OUTPUT)
C1
J1
tOD(2)
ADATA(7-0)
APAR
h2
h3
A1
A2
J1
R=00
R=00
DATA
C1 = 01
DATA
h1
(OUTPUTS)
ADD
(OUTPUT)
(LOW)
Note: Timing is shown for STS-1 signal. Pointer value is transmitted with a
value equal to 0. When the TOHOUT bit is set to 1, the A1, A2, C1, H1,
and H2 bytes are generated. Different from add/drop mode, output
AC1J1/ASPE and ADATA are synchronous in the external clock mode.
Parameter
Symbol
Min
Typ
Max
Unit
XCLKI clock period
tCYC(1)
--
tCYC(2)
--
tOD(1)
tOD(2)
154.32
50
ns
%
XCLKI duty cycle, tPWH(1)/tCYC(2)
ACLK clock period
40
60
154.32
50
ns
%
ACLK duty cycle, tPWH(2)/tCYC(2)
AC1J1/ASPE delay after ACLK↑
40
0.0
0.0
60
5.0
12
ns
ns
ADATA(7-0) data and APAR delay after
ACLK↑
ACLK↑ clock delay after XCLKI↑
tOD(3)
3.0
25
ns
TXC-03452B-MB
Ed. 6, April 2001
- 35 of 96 -
ETC [ ETC ]
