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L3M
TXC-03452B
DATA SHEET
Figure 9. STM-1 Add Bus Derived Interface Timing
tCYC
tPWH
ACLK
(INPUT)
tH(2)
tSU(2)
ASPE
(INPUT)
tOD(1)
tH(1)
AC1J1
(INPUT)
tSU(1)
tOD(3)
C1(1)
J1
ADATA (7-0)
APAR
(OUTPUTS)
STUFF
BYTE
FOR J1
H1
TUG-3
DATA
tOD(2)
tOD(4)
ADD
(OUTPUT)
Note: The relationship between J1 and the SPE signal is shown for illustration purposes
only. For the STM-1 format, there will be one J1 pulse which indicates the start of
the VC-4 that carries the three TUG-3s. The TUG-3 added to the bus is shown for
the TUG-3 designated as A. TUG-3 B will occur one clock cycle later. There is
always a one byte delay between the output ADATA and AC1J1/ASPE inputs.
Parameter
Symbol
Min
Typ
Max
Unit
ACLK clock period
tCYC
--
51.44
50
ns
%
ACLK duty cycle, tPWH/tCYC
AC1J1 set-up time to ACLK↓
AC1J1 hold time after ACLK↓
ASPE set-up time to ACLK↓
ASPE hold time after ACLK↓
40
7.0
3.0
10.0
5.0
3.0
60
30
tSU(1)
tH(1)
tSU(2)
tH(2)
tOD(1)
ns
ns
ns
ns
ns
ADATA(7-0) data and APAR output delay
from ACLK↑
ADD low output delay from ACLK↑
tOD(2)
tOD(3)
3.0
12
25
25
ns
ns
ADATA(7-0) and APAR tri-state delay from
ACLK↑
ADD high output delay from ACLK↑
tOD(4)
12
25
ns
TXC-03452B-MB
Ed. 6, April 2001
- 29 of 96 -
ETC [ ETC ]
