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L3M
TXC-03452B
DATA SHEET
Figure 17. STS-3 Add/Drop Bus Interface Timing
tCYC
tPWH
DCLK
(INPUT)
tH(1)
tSU(1)
DDATA(7-0)
DPAR
FIXED
STUFF
FIXED
STUFF
C1(1)
C1(2)
C1(3)
J1
DATA
DATA
DATA
(INPUTS)
tH(2)
tSU(2)
DSPE
(INPUT)
tH(1)
tSU(1)
DC1J1
(INPUT)
C1(1)
J1
tOD(3)
tOD(1)
ADATA(7-0)
APAR
J1
DATA
DATA
(OUTPUTS)
tOD(2)
ADD
(OUTPUT)
tOD(4)
Note: The relationship between J1 and the SPE signals is shown for illustration purposes only,
and will be a function of the pointer offset. For the STS-3 format, there will be three J1
pulses with each J1 pulse indicating the start of an STS-1. The C1 pulse is shown dotted
because the C1 pulse may be provided on the DC1 signal lead. If the DC1 signal lead is
not used, it must be grounded. Shown is STS-1 number 1 being added to the Add bus.
Parameter
DCLK clock period
Symbol
Min
Typ
Max
Unit
tCYC
--
51.44
50
ns
%
DCLK duty cycle, tPWH/tCYC
40
60
DDATA(7-0) data/DPAR/DC1J1 set-up
tSU(1)
7.0
ns
time to DCLK↓
DDATA(7-0) data/DPAR/DC1J1 hold time
tH(1)
3.0
ns
after DCLK↓
DSPE set-up time to DCLK↓
DSPE hold time after DCLK↓
tSU(2)
tH(2)
10.0
5.0
ns
ns
ns
ADATA(7-0) data and APAR delay after
tOD(1)
3.0
30
DCLK↑
ADD indicator delayed after DCLK↑
tOD(2)
tOD(3)
3.0
12
25
25
ns
ns
ADATA(7-0) data and APAR tri-state after
DCLK↑
ADD indicator high after DCLK↑
tOD(4)
12
25
ns
TXC-03452B-MB
Ed. 6, April 2001
- 37 of 96 -
ETC [ ETC ]
