APEX 20K Programmable Logic Device Family Data Sheet
Table 15. APEX 20K ClockLock & ClockBoost Parameters for -1 Speed-Grade
Devices (Part 2 of 2)
Symbol
Parameter
Min
Max
Unit
tLOCK
Time required for
10
µs
ClockLock/ClockBoost to acquire
lock(4)
tSKEW
Skew delay between related
ClockLock/ClockBoost-generated
clocks
500
ps
tJITTER
Jitter on ClockLock/ClockBoost-
200
50
ps
ps
generated clock (5)
tINCLKSTB
Input clock stability (measured
between adjacent clocks)
Notes:
(1) The PLL input frequency range for the EP20K100-1X device for 1x multiplication is
25 MHz to 175 MHz.
(2) All input clock specifications must be met. The PLL may not lock onto an incoming
clock if the clock specifications are not met, creating an erroneous clock within the
device.
(3) During device configuration, the ClockLock and ClockBoost circuitry is configured
first. If the incoming clock is supplied during configuration, the ClockLock and
ClockBoost circuitry locks during configuration, because the lock time is less than
the configuration time.
(4) The jitter specification is measured under long-term observation.
(5) If the input clock stability is 100 ps, t
is 250 ps.
JITTER
Altera Corporation
51
ETC [ ETC ]
