Si3210/Si3211/Si3212
Table 11. Switching Characteristics—PCM Highway Serial Interface
V
= 3.13 to 5.25 V, T = 0 to 70°C for K-Grade, –40 to 85°C for B-Grade, C = 20 pF
D
A
L
Parameter
Test
Conditions
1
1
1
Symbol
Units
Min
Typ
Max
PCLK Frequency
1/t
—
—
—
—
—
—
—
—
40
0.256
0.512
0.768
1.024
1.536
2.048
4.096
8.192
50
—
—
—
—
—
—
—
—
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
%
c
PCLK Duty Cycle Tolerance
PCLK Period Jitter Tolerance
Rise Time, PCLK
t
60
120
25
25
20
20
dty
t
–120
—
—
ns
jitter
t
—
ns
r
Fall Time, PCLK
t
—
—
ns
f
Delay Time, PCLK Rise to DTX Active
t
—
—
ns
d1
d2
Delay Time, PCLK Rise to DTX
Transition
t
—
—
ns
2
Delay Time, PCLK Rise to DTX Tri-state
Setup Time, FSYNC to PCLK Fall
Hold Time, FSYNC to PCLK Fall
Setup Time, DRX to PCLK Fall
Hold Time, DRX to PCLK Fall
Notes:
t
—
25
20
25
20
—
—
—
—
—
20
—
—
—
—
ns
ns
ns
ns
ns
d3
t
su1
t
h1
t
su2
t
h2
1. All timing is referenced to the 50% level of the waveform. Input test levels are V
2. Spec applies to PCLK fall to DTX tri-state when that mode is selected (TRI = 0).
V
0.4V, V = 0.4V
IH – I/O –
IL
tr
tf
tc
PCLK
th1
tsu1
FSYNC
tsu2
th2
DRX
DTX
td2
td1
td3
Figure 8. PCM Highway Interface Timing Diagram
Preliminary Rev. 1.11
15
ETC [ ETC ]
