Functional Description
Refer to Section 4.8, “Power Management” on page 4-28 for more details on SMRAM support.
Reiteration:
• Only un-cacheable SMM regions may overlap PCI or AGP Windows.
• SMM regions will not overlap the AGP aperture.
• Software (not in SMM) will not access PCI memory behind cacheable SMM regions.
• PCI or AGP masters cannot access the SMM space.
4.1.2
4.1.3
Memory Shadowing
Any block of memory that can be designated as read-only or write-only can be “shadowed” into
82443BX DRAM memory. Typically, this is done to allow ROM code to execute more rapidly out
of main DRAM. ROM is used as a read-only during the copy process while DRAM at the same
time is designated write-only. After copying, the DRAM is designated read-only so that ROM is
shadowed. CPU bus transactions are routed accordingly.
I/O Address Space
The 82443BX does not support the existence of any other I/O devices besides itself on the CPU
bus. The 82443BX generates either PCI or AGP bus cycles for all CPU I/O accesses. The 82443BX
contains three internal registers in the CPU I/O space, Configuration Address Register
(CONFIG_ADDRESS) and the Configuration Data Register (CONFIG_DATA) and Power
Management Control Register. These locations are used to implement PCI configuration space
access mechanism and as described in Section 3.1, “I/O Mapped Registers” on page 3-2.
The CPU allows 64K+3 bytes to be addressed within the I/O space. The 82443BX propagates the
CPU I/O address without any translation on to the destination bus and therefore provides
addressability for 64K+3 byte locations. Note that the upper 3 locations can be accessed only
during I/O address wrap-around when CPU bus A16# address signal is asserted. A16# is asserted
on the CPU bus whenever an I/O access is made to 4 bytes from address 0FFFDh, 0FFFEh, or
0FFFFh. A16# is also asserted when an I/O access is made to 2 bytes from address 0FFFFh.
The I/O accesses (other than ones used for PCI configuration space access) are forwarded normally
to the PCI bus unless they fall within the PCI1/AGP I/O address range as defined by the
mechanisms in Section 4.1.4. The 82443BX will not post I/O write cycles to IDE.
4.1.4
AGP I/O Address Mapping
The 82443BX can be programmed to direct non-memory (I/O) accesses to the AGP bus interface
when CPU-initiated I/O cycle addresses are within the AGP I/O address range. This range is
controlled via the I/O Base Address (IOBASE) and I/O Limit Address (IOLIMIT) registers in
82443BX Device #1 configuration space.
The 82443BX positively decodes I/O accesses to AGP I/O address space as defined by the
following equation:
≤
≤
I/O_Base_Address CPU I/O Cycle Address I/O_Limit_Address
The effective size of the range is programmed by the plug-and-play configuration software and it
depends on the size of I/O space claimed by the AGP compliant device.
4-8
82443BX Host Bridge Datasheet
ETC [ ETC ]
