Functional Description
Table 4-6. Host Responses supported by the 82443BX
RS2#
RS1#
RS0#
Description
82443BX Support
0
0
0
idle
To avoid deadlock, this response is generated when a
resource cannot currently be accessed by the
processor. PCI-directed reads, writes, DRAM locked
reads, AGP reads and writes can be retried.
0
0
0
1
1
0
Retry Response
This response can be returned for all transactions that
can be executed ‘out of order.’ PCI-directed reads
(memory, I/O and Interrupt Acknowledge) and writes
(I/O only), and AGP directed reads (memory and I/O)
and writes (I/O only) can be deferred.
Deferred Response
0
1
1
0
1
0
Reserved
Reserved
Hard Failure
Not supported.
This is for transactions where the data has already
been transferred or for transactions where no data is
transferred. Writes and zero length reads receive this
response.
1
0
1
No Data Response
Implicit Writeback
This response is given for those transactions where
the initial transactions snoop hits on a modified cache
line.
1
1
1
1
0
1
This response is for transactions where data
accompanies the response phase. Reads receive this
response.
Normal Data
Response
Special Cycles
A Special Cycle is defined when REQa[4:0] = 01000 and REQb[4:0]= xx001. The first address
phase Aa[35:3]# is undefined and can be driven to any value. The second address phase, Ab[15:8]#
defines the type of Special Cycle issued by the processor.
Table 4-3 specifies the cycle type and definition as well as the action taken by the 82443BX when
the corresponding cycles are identified.
Table 4-7. Host Special Cycles with 82443BX
Special
Cycle Type
BE[7:0}#
Action Taken
0000
0000
NOP
This transaction has no side-effects.
This transaction is issued when an agent detects a severe software error that
prevents further processing. This cycle is claimed by the 82443BX. The 82443BX
issues a shutdown special cycle on the PCI bus. This cycle is retired on the CPU
bus after it is terminated on the PCI via a master abort mechanism.
0000
0001
Shutdown
Flush
This transaction is issued when an agent has invalidated its internal caches
without writing back any modified lines. The 82443BX claims this cycle and
retires it.
0000
0010
This transaction is issued when an agent executes a HLT instruction and stops
program execution. This cycle is claimed by the 82443BX and propagated to PCI
as a Special Halt Cycle. This cycle is retired on the CPU bus after it is terminated
on the PCI via a master abort mechanism.
0000
0011
Halt
0000
0100
This transaction is issued when an agent has written back all modified lines and
has invalidated its internal caches. The 82443BX claims this cycle and retires it.
Sync
4-12
82443BX Host Bridge Datasheet
ETC [ ETC ]
