Functional Description
Table 4-5. Host Bus Transactions Supported By 82443BX
Transaction
Deferred Reply
REQA[4:0]#
REQB[4:0]#
X X X X X
82443BX Support
The 82443BX initiates a deferred reply for a
previously deferred transaction.
0 0 0 0 0
0 0 0 0 1
0 1 0 0 0
Reserved
X X X X X
0 0 0 0 0
Reserved
Interrupt acknowledge cycles are forwarded to
the PCI bus.
Interrupt Acknowledge
Special Transactions
Reserved
0 1 0 0 0
0 1 0 0 0
0 1 0 0 0
0 0 0 0 1
0 0 0 1 x
0 0 1 x x
See separate table in Special Cycles section.
Reserved
Reserved
Reserved
The 82443BX terminates a branch trace
message without latching data.
Branch Trace Message
0 1 0 0 1
0 0 0 0 0
Reserved
Reserved
Reserved
0 1 0 0 1
0 1 0 0 1
0 1 0 0 1
0 0 0 0 1
0 0 0 1 x
0 0 1 x x
Reserved
Reserved
Reserved
I/O read cycles are forwarded to PCI or AGP.
I/O cycles which are in the 82443BX
I/O Read
1 0 0 0 0
0 0 x LEN#
configuration space are not forwarded to PCI.
I/O write cycles are forwarded to PCI or AGP.
I/O cycles which are in the 82443BX
configuration space are not forwarded to PCI.
I/O Write
Reserved
1 0 0 0 1
1 1 0 0 x
0 0 x LEN#
0 0 x x x
Reserved
Host initiated memory read cycles are
forwarded to DRAM or the PCI/1 bus. The
82443BX initiates an MRI cycle for a PCI/1
initiated write cycle to DRAM.
Memory Read &
Invalidate
0 0 0 1 0
0 0 x LEN#
Reserved
0 0 0 1 1
0 0 1 0 0
0 0 x LEN#
0 0 x LEN#
Reserved
Memory code read cycles are forwarded to
DRAM or PCI/1.
Memory Code Read
Host initiated memory read cycles are
forwarded to DRAM or the PCI/1 bus. The
82443BX initiates a memory read cycle for a
PCI/1 initiated read cycle to DRAM.
Memory Data Read
0 0 1 1 0
0 0 x LEN#
This memory write is a writeback cycle and
cannot be retried. The 82443BX forwards the
write to DRAM.
Memory Write (no retry) 0 0 1 0 1
0 0 x LEN#
0 0 x LEN#
Memory Write (can be
0 0 1 1 1
The normal memory write cycle is forwarded
to DRAM or PCI/1.
retried)
NOTE:
1. For Memory cycles, REQa[4:3]# = ASZ#. The 82443BX only supports ASZ# = 00 (32 bit address).
®
2. REQb[4:3]# = DSZ#. For the Pentium Pro processor, DSZ# = 00 (64 bit data bus size).
3. LEN# = data transfer length as follows:
LEN#
Data length
00
01
10
11
≤ 8 bytes (BE[7:0]# specify granularity)
Length = 16 bytes BE[7:0]# all active
Length = 32 bytes BE[7:0]# all active
Reserved
82443BX Host Bridge Datasheet
4-11
ETC [ ETC ]
