Functional Description
4.1.1.1
Compatibility Area
This area is divided into the following address regions:
• 0–512 KB DOS Area
• 512 KB – 640 KB DOS Area - Optional ISA/PCI Memory
• 640KB – 768 KB Video Buffer Area
• 768 KB – 896 KB in 16KB sections (total of 8 sections) - Expansion Area
• 896KB – 960 KB in 16KB sections (total of 4 sections) - Extended System BIOS Area
• 960 KB – 1 MB Memory (BIOS Area) - System BIOS Area
There are sixteen memory segments in the compatibility area. Thirteen of the memory ranges can
be enabled or disabled independently for both read and write cycles. One segment
(512 KB–640 KB) which can be mapped to either main DRAM or PCI.
Table 4-1. Memory Segments and their Attributes
Memory Segments
000000h–07FFFFh
Attributes
Comments
fixed - always mapped to main DRAM
configurable as PCI or main DRAM
0 – 512 KB; DOS Region
080000h–09FFFFh
512 KB – 640 KB; DOS Region
mapped to PCI - configurable as SMM Video Buffer (physical DRAM
0A0000h–0BFFFFh
space
configurable as SMM space)
0C0000h–0C3FFFh
0C4000h–0C7FFFh
0C8000h–0CBFFFh
0CC000h–0CFFFFh
0D0000h–0D3FFFh
0D4000h–0D7FFFh
0D8000h–0DBFFFh
0DC000h–0DFFFFh
0E0000h–0E3FFFh
0E4000h–0E7FFFh
0E8000h–0EBFFFh
0EC000h–0EFFFFh
0F0000h–0FFFFFh
WE; RE
WE; RE
WE; RE
WE; RE
WE; RE
WE; RE
WE; RE
WE; RE
WE; RE
WE; RE
WE; RE
WE; RE
WE; RE
Add-on BIOS
Add-on BIOS
Add-on BIOS
Add-on BIOS
Add-on BIOS
Add-on BIOS
Add-on BIOS
Add-on BIOS
BIOS Extension
BIOS Extension
BIOS Extension
BIOS Extension
BIOS Area
DOS Area (00000h–9FFFh)
The DOS area is 640 KB and it is further divided into two parts. The 512 KB area at 0 to 7FFFFh is
always mapped to the main memory controlled by the 82443BX, while the 128 KB address range
from 080000 to 09FFFFh can be mapped to PCI or to main DRAM. By default this range is
mapped to main memory and can be declared as a main memory hole (accesses forwarded to PCI)
via the 82443BX’s FDHC configuration register.
Video Buffer Area (A0000h–BFFFFh)
The 128 KB graphics adapter memory region is normally mapped to a legacy video device on PCI
(typically VGA controller). This area is not controlled by attribute bits and CPU-initiated cycles in
this region are forwarded to PCI or AGP for termination. This region is also the default region for
SMM space.
The SMRAM Control register controls how SMM accesses to this space are treated.
82443BX Host Bridge Datasheet
4-3
ETC [ ETC ]
