Version: 1.18
PRELIMINARY/CONFIDENTIAL
TrueSpeech® Co-Processor
RX DMA Enable:
Setting this bit to 1 enables the RXDREQ and RXDACKN signals. If this bit is set to
zero, the RXDACKN signal is ignored and the RXDREQ signal is not asserted. This
control operates on the logical RX DMA signals, not the physical pins whose functions
can be exchanged between RX and TX. After reset, this bit is zero.
HOST IRQN
Master Enable
Setting this bit to 1 enables the IRQN output signal. If this bit is not set the IRQN signal
is not asserted. After reset, this bit is zero.
Aux Status Update IE:
Status Update IE:
TX Ready IE:
If this bit is set, the Host IRQN signal is asserted whenever the Aux Status Ready bit in
the Hardware Status Register is set. After reset, this bit is zero.
If this bit is set, the Host IRQN signal is asserted whenever the Status Ready bit in the
Hardware Status Register is set. After reset, this bit is zero.
If this bit is set, the Host IRQN signal is asserted whenever the TX Ready bit in the
Hardware Status Register is set. After reset, this bit is zero.
RX Ready IE:
If this bit is set, the Host IRQN signal is asserted whenever the RX Ready bit in the
Hardware Status Register is set. After reset, this bit is zero.
CONTINUE:
The Host writes a 1 to this bit to clear the COHOST SHUTDOWN bit in the Hardware
Status Register. This returns the Host and CODEC logic to normal operation from sleep
mode. This bit always reads as a 0.
When COHOST SHUTDOWN is in operation, only the continue bit in the Hardware
Control Register is accessible. All other bits are undefined for read and write operations.
COHOST SHUTDOWN is a power save state where the CODEC and HOST sections of
the CT8022 are disabled in order to reduce power consumption. In this state it is still
possible for the CT8022 DSP core to remain active.
CT8022A11AQC FW Revision 0118 DSP GROUP, INC., 3120 SCOTT BOULEVARD
SANTA CLARA, CA 95054 PH: 408 986 – 4300 FAX: 408 986 – 4490
29
All specifications are subject to change without prior notice.
ETC [ ETC ]
