Version: 1.18
PRELIMINARY/CONFIDENTIAL
TrueSpeech® Co-Processor
4.4
Host Programmers Model
Host Byte
Address
HSTAB3-0
Host Word
Address
HSTAB3-1
Function
Access
0-1
2-3
4-5
6-7
8-9
A-B
C-D
E-F
0
1
2
3
4
5
6
7
Aux Software Status Register (Reserved)
Software Status Register
Aux Software Control Register (Reserved)
Software Control Register
Hardware Status Register
Hardware Control Register
Read Only
Read Only
Read/Write
Read/Write
Read Only
Read/Write
Host Transmit (Write) Data Buffer Access Port (buffer input)
Host Receive (Read) Data Buffer Access Port (buffer output)
Write Only
Read Only
Note that the CT8022 registers are all internally 16-bits wide. Physical access to these registers is accomplished
using two 8-bit access cycles via the Host Interface. The lower byte of each register is accessed when address line
HSTAB0 = 0. The upper byte of each register is accessed when address line HSTAB0 = 1. The registers should
always be accessed low byte first followed by high byte. Accesses to the upper byte of the Software Status, Software
Control, and Data Buffer Access Port Registers trigger certain internal events within the CT8022. For example,
reading the upper byte of the Software Status Register clears the Status Ready bit in the Hardware Status Register.
CT8022A11AQC FW Revision 0118 DSP GROUP, INC., 3120 SCOTT BOULEVARD
SANTA CLARA, CA 95054 PH: 408 986 – 4300 FAX: 408 986 – 4490
27
All specifications are subject to change without prior notice.
ETC [ ETC ]
