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CT8022A11AQC 参数 Datasheet PDF下载

CT8022A11AQC图片预览
型号: CT8022A11AQC
PDF下载: 下载PDF文件 查看货源
内容描述: VOIP / VON G.723.1 , G279AB TRUESPEECH协处理器 [VOIP/VON G.723.1, G279AB TRUESPEECH CO-PROCESSOR]
分类和应用:
文件页数/大小: 194 页 / 1455 K
品牌: ETC [ ETC ]
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TrueSpeech® Co-Processor  
PRELIMINARY/CONFIDENTIAL  
Version: 1.18  
4.5.5  
Host Receive and Transmit Data Buffer Blocks  
The CT8022 includes two 16-word (32 byte) data buffer blocks for use in transferring blocks of data to or from the  
Host. Access to these buffers is controlled by the CT8022. The Host accesses these buffers in sequential address  
order through two 16-bit Host Data Buffer access ports (one for RX and one for TX). The Host address sequence is  
generated by an internal address counter within the CT8022.  
Each buffer is shared between the Host and CT8022. At any one time, either the Host or the CT8022 has access to  
the buffer. At no time can both Host and CT8022 access the buffer simultaneously. The CT8022 controls whether  
access belongs to the CT8022 or Host via an internal control register. For example, when the Host transmits data to  
the CT8022, the CT8022 first grants the Host access to the buffer. The Host fills the empty buffer. While the Host  
is filling the buffer, the CT8022 can not access it. Once the buffer is full, the CT8022 regains access to the full  
buffer. The CT8022 then copies the data from the buffer. At this point, the Host can not access the buffer. Once the  
buffer has been emptied, the CT8022 can then pass it back to the Host.  
The receive and transmit buffer blocks are conceptually almost identical except for the direction of data transfer  
associated with Host accesses. The receive buffer is used to transfer data from the CT8022 to the Host. The  
transmit buffer is used to transfer data from the Host to the CT8022.  
4.5.5.1  
Host Receive Data Buffer Block  
This block is used to transfer data from the CT8022 to the Host, using an external DMA controller or a Host  
processor access cycle.  
HSTRD  
DMA byte  
Select  
Toggle  
Data  
Host Access Port  
Data  
16 x 16  
Data Buffer  
Address  
Address  
Counter  
Address  
Comparator  
Internal Control Register  
Control  
RX Ready  
Frame Size  
RX Ready  
RXDREQ  
DMA Logic  
Figure 4-2:  
Host Receive Data Buffer Block  
32  
DSP GROUP, INC., 3120 SCOTT BOULEVARD CT8022A11AQC FW Revision 0118  
SANTA CLARA, CA 95054 PH: 408 986 – 4300 FAX: 408 986 – 4490  
All specifications are subject to change without prior notice.  
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