TrueSpeech® Co-Processor
PRELIMINARY/CONFIDENTIAL
Version: 1.18
4.5.2
Hardware Status Register
This register is read only accessible by the Host.
0
0
0
0
0
COHOST
SHUTDOWN
TX DMA
(9)
RX DMA
(8)
(15)
(14)
(13)
(12)
(11)
(10)
IRQN
Asserted
SYSTEM
RESTART
TX Ready RX Ready Aux Status
Ready
Status Ready
(2)
Aux Control
Ready
Control Ready
(0)
(7)
(6)
(5)
(4)
(3)
(1)
SYSTEM RESTART:
TX Ready:
Reserved
This bit reflects the state of the TX Ready bit in the DSP’s Host Transmit Buffer control
register. This bit is set to indicate that the Host Transmit Data Buffer can be accessed by
the Host. When the Host writes to the high byte of the Host Transmit Data Buffer access
port and the Frame Size limit is reached (buffer full), this bit is cleared. After reset, this
bit is clear.
When this bit is set and the TX Ready IE bit in the Hardware Control Register is set, the
Host IRQN signal is asserted.
TX DMA:
RX Ready:
This bit is set if the (logical) TXDREQ signal is asserted. The state of this bit is affected
by the TX DMA enable bit in the Host interface hardware control register. If the TX
DMA enable is not set, this bit will always be zero.
This bit reflects the state of the RX Ready bit in the DSP’s Host Receive Buffer control
register. This bit is set to indicate that the Host Receive Data Buffer can be accessed by
the Host. When the Host reads from the high byte of the Host Receive Buffer access port,
and the Frame Size limit is reached (buffer empty), this bit is cleared. After reset, this bit
is clear.
When this bit is set and the RX Ready IE bit in the Hardware Control Register is set, the
Host IRQN signal is asserted.
RX DMA:
This bit is set if the (logical) RXDREQ signal is asserted. The state of this bit is affected
by the RX DMA enable bit in the Host interface hardware control register. If the RX
DMA enable is not set, this bit will always be zero.
Status Ready:
This bit is set when the Oak core writes to the Software Status Register. When the Host
reads the high byte of the Software Status Register, this bit is cleared. After reset, this bit
is cleared.
When this bit is set and the Status Ready IE bit in the Hardware Control Register is set,
the Host IRQN signal is asserted.
IRQN Asserted:
This bit reflects the state of the external IRQN pin. If the IRQN signal is asserted, this bit
is set. If the Host IRQN Master Enable is not set, this bit will always be zero.
30
DSP GROUP, INC., 3120 SCOTT BOULEVARD CT8022A11AQC FW Revision 0118
SANTA CLARA, CA 95054 PH: 408 986 – 4300 FAX: 408 986 – 4490
All specifications are subject to change without prior notice.
ETC [ ETC ]
