Version: 1.18
PRELIMINARY/CONFIDENTIAL
TrueSpeech® Co-Processor
4.5.5.1.1
Receive Data Buffer Internal Control Register
This is an internal register, and is not accessible by the Host.
0000 0000
(15-8)
RX Ready
(7)
00
Frame Size
(4-0)
(6-5)
RX Ready:
When set to zero, the CT8022 has control of the data buffer and has write only access to
any location in the buffer.
When set to one, the Host has control of the data buffer and may read its contents via the
Host Data Buffer access port.
The state of this bit can be checked by the Host at any time since it is reflected by the RX
Ready bit in the Hardware Status register. The RX Ready bit in the Receive Data Buffer
Control Register drives the RX Ready bit and also RXDREQ via the DMA logic.
After reset, this bit is zero.
Frame Size:
The Frame Size field determines the number of words contained in the data buffer. It acts
as the reference input to the Host buffer address comparator.
Address Counter
The 5-bit address counter provides the sequential buffer access address for access by the Host via the Host Data
Buffer access port. The address counter is reset to zero when the CT8022 writes a 1 to the RX Ready bit of the
internal control register causing control of the buffer to transfer to the Host. Each time the Host accesses the upper
byte of the Host Data Buffer access port the address counter increments by 1.
The data buffer access port is only physically 8-bits wide. When an access to this port is made by a Host processor,
the byte select address line HSTAB0 is valid and can be used to select the byte accessed. When access is made by a
DMA controller, the address decode which selects the data buffer access port is provided by the RXDACKN signal.
During a DMA cycle, the HSTAB3-0 address bits are not valid. Generation of an internal HSTAB0 is thus required
to select the byte accessed. This is provided by a simple toggle mechanism that changes state on each DMA access.
The DMA byte select toggle is set to zero each time the RX Ready bit changes from a zero to a one (this also clears
the main address counter). A separate DMA byte select toggle is required for transmit and receive.
Comparator
The 5-bit comparator is active only when the Host has control (the RX Ready bit is set). The comparator compares
the value in the address counter with the value in the Frame Size field. If the values are not equal, the Host continues
to have access to the data buffer. When the values become equal (after the last Host access), the RX Ready bit is
reset, transferring control back to the CT8022.
Transferring Data From CT8022 To Host
The CT8022 determines the size of the data frame to be transferred by some protocol with the Host. At the
beginning of data transfer, the RX Ready bit will be zero. The CT8022 then writes the appropriate number of words
into the data buffer. It then programs the Frame Size and sets the RX Ready bit. This causes the RX Ready bit,
visible to the Host n the Hardware Status Register, to be set. The Host discovers that the RX Ready bit is set (by
polling or interrupt). The Host then reads Frame Size words from the Host Receive Buffer Access Port, after each
word is read, the address counter increments. When the Host reads the last word, the address counter is incremented
and matches the Frame Size value. This is detected by the comparator, which causes the RX Ready bit to be cleared.
The CT8022 determines that it has access to the data buffer and loads the next frame into the buffer. This process is
repeated to transfer the next frame.
For DMA transfers, the RX Ready bit drives the state of the DMA Request signal. When RX Ready is set, the DMA
request is asserted. When the buffer becomes empty, and buffer control automatically returns to the CT8022, the RX
Ready bit is cleared and the DMA Request signal is de-asserted.
CT8022A11AQC FW Revision 0118 DSP GROUP, INC., 3120 SCOTT BOULEVARD
SANTA CLARA, CA 95054 PH: 408 986 – 4300 FAX: 408 986 – 4490
33
All specifications are subject to change without prior notice.
ETC [ ETC ]
