TrueSpeech® Co-Processor
PRELIMINARY/CONFIDENTIAL
Version: 1.18
4.5
Register Descriptions
4.5.1
Hardware Control Register
This register has read/write access from the Host.
0
0
0
0
0
Host IRQN
Master Enable
CONTINUE
(9)
DMA Direction
(8)
(15)
(14)
(13)
(12)
(11)
(10)
TX DMA
Burst Mode Burst Mode
RX DMA
TX DMA
Enable
RX DMA Aux Status Status Update IE
TX Ready IE
(1)
RX Ready IE
(0)
Enable
Update IE
(7) (6)
(5)
(4)
(3)
(2)
TX DMA Burst Mode:
RX DMA Burst Mode:
DMA Direction:
When this bit is set, the TX DMA interface operates in Burst Mode. In Burst Mode, the
TXDREQ signal is continuously asserted if the TX Ready bit for the Host Transmit buffer
is set.
When this bit is clear, the TX DMA interface operates in Single Cycle Mode. In Single
Cycle Mode, the TXDREQ signal is de-asserted every time the TXDACKN and
HSTWRN signals are asserted, then re-asserted if the TX Ready bit is still set, after a
delay (buffer not full). Refer to Section 4.6.
When this bit is set, the RX DMA interface operates in Burst Mode. In Burst Mode, the
RXDREQ signal is continuously asserted if the RX Ready bit for the Host Receive buffer
is set.
When this bit is clear, the RX DMA interface operates in Single Cycle Mode. In Single
Cycle Mode, the RXDREQ signal is de-asserted every time the RXDACKN and
HSTRDN signals are asserted, then re-asserted if the RX Ready bit for the Host Receive
Buffer is still set, after a delay (buffer not empty). Refer to Section 4.6.
This field allows the Host to use the DMA features in a full duplex or half duplex
configuration. In a half-duplex configuration, the Host needs to interface a single DMA
channel to the CT8022, and needs to be able to transfer data in either direction with this
single channel. This is accommodated within the CT8022 by permitting the functional
exchange of the external (physical) DMA interface pins. Refer to Section 4.6.
0
1
Normal Direction. The TXDREQ, RXDREQ, TXDACKN and RXDACKN operate in
the manner described in the CT8022 pin out. After reset, this bit is set to zero.
Reverse Direction. The physical pin functions of TXDREQ and RXDREQ, and also
TXDACKN and RXDACKN are exchanged, i.e. the TXDREQ pin assumes the function
and behavior of the RXDREQ pin and vice-versa. Refer to Section 4.6.1.2.
TX DMA Enable:
Setting this bit to 1 enables the TXDREQ and TXDACKN signals. If this bit is set to
zero, the TXDACKN signal is ignored and the TXDREQ signal is not asserted. This
control operates on the logical TX DMA signals, not the physical pins whose functions
can be exchanged between RX and TX. After reset, this bit is zero.
28
DSP GROUP, INC., 3120 SCOTT BOULEVARD CT8022A11AQC FW Revision 0118
SANTA CLARA, CA 95054 PH: 408 986 – 4300 FAX: 408 986 – 4490
All specifications are subject to change without prior notice.
ETC [ ETC ]
