Version: 1.18
PRELIMINARY/CONFIDENTIAL
TrueSpeech® Co-Processor
Control Ready:
This bit is set when the Oak core reads from the Software Control Register. When the
Host writes to the high order byte of the Software Control Register, this bit is cleared.
After reset, this bit is cleared to indicate that the CT8022 is not ready to receive
commands. Once the CT8022 is ready to begin communication with the Host, it performs
a dummy read of the Software Control Register to set the Control Ready bit.
Aux Status Ready:
Aux Control Ready:
This bit is set when the Oak core writes to the Aux Software Status Register. When the
Host reads the high byte of the Aux Software Status Register, this bit is cleared. After
reset, this bit is cleared.
When this bit is set and the Aux Status Ready IE bit in the Hardware Control Register is
set, the Host IRQN signal is asserted.
This bit is set when the Oak core reads from the Aux Software Control Register. When
the Host writes to the high order byte of the Aux Software Control Register, this bit is
cleared. After reset, this bit is cleared to indicate that the CT8022 is not ready to receive
commands. Once the CT8022 is ready to begin communication with the Host, it performs
a dummy read of the Aux Software Control Register to set the Aux Control Ready bit.
COHOST SHUTDOWN: This bit indicates that the CODEC and Host interface logic is in sleep mode (power save).
The Host interface must be re-awakened by writing to the CONTINUE bit in the
Hardware Control Register before writing or reading from any other Host register. When
COHOST SHUTDOWN is active, all the other bits in the Hardware Status Register are
undefined for read operations.
4.5.3
Software Control Register
This is a 16-bit register. It is used to pass commands from the Host to the CT8022. The Host can write commands
to this register, and read back the command, after it has been written.
When the Host writes to the upper byte of this register, it clears the Control Ready bit in the Hardware Status
Register.
When the CT8022 internally reads from this register, it sets the Control Ready bit in the Hardware Status Register.
The CT8022 hardware includes a second Aux Software Control Register. This register is reserved and is not used by
the internal CT8022 firmware.
4.5.4
Software Status Register
This is a 16-bit register. It is used to pass command status/result information from the CT8022 back to the Host.
The Host can only read from this register.
When the CT8022 updates this register, it sets the Status Ready bit in the Hardware Status Register and also asserts
IRQN to the Host (if enabled).
When the Host reads the upper byte of this register, it clears the Status Ready Hardware Status Register. The IRQN
will also clear at this time, if enabled.
The CT8022 hardware includes a second Aux Software Status Register. This register may be used to provide an
independent status register for reporting the status of the DTMF and Call Progress Tone detector. This allows the
CT8022 to provide an interrupt on DTMF feature when used in conjunction with the interrupt enable controls in the
Hardware Control Register.
CT8022A11AQC FW Revision 0118 DSP GROUP, INC., 3120 SCOTT BOULEVARD
SANTA CLARA, CA 95054 PH: 408 986 – 4300 FAX: 408 986 – 4490
31
All specifications are subject to change without prior notice.
ETC [ ETC ]
