TrueSpeech® Co-Processor
PRELIMINARY/CONFIDENTIAL
Version: 1.18
3.22
8/16-bit Host Controller Interface
The operation of the CT8022 is controlled via 8 16-bit registers that provide a control/status/data interface. This
interface is accessed physically as 16 8-bit wide I/O locations mapped to the Host controller address space. This
allows the CT8022 to be used with inexpensive 8-bit micro-controllers or more powerful 16/32 bit microprocessors.
The Host controls the CT8022 by writing control words to the CT8022 registers and it obtains status information by
reading the CT8022 status registers. Speech data is passed through the receive/transmit buffer registers when
recording or playing speech data to or from the Host. Receive and transmit data buffers are 16 words deep and
Host-controllable. In addition, CT8022 provides either single-cycle or continuous (burst) DMA modes for both
half-duplex and full-duplex speech transfers.
3.23
CODEC Interface
The CT8022 supports direct connection to one or two external 8-bit G.711 A-law/µ-law or 16-bit Linear CODECs
for input and output of audio signals. If two CODECs are used, both CODECs must be of the same type. The
CT8022 can act as a CODEC clock master, or it can be driven by an external CODEC clock. In master mode, the
CODEC clock SCLK and FSYNC signals are generated by programmable integer division from the internal CT8022
clock.
3.24
CT8022 Crystal
The CT8022 includes a clock frequency multiplying PLL (Phase Locked Loop) to avoid requiring a high frequency
external clock source for generation of the internal 45.056 MHz CT8022 clock. The PLL allows generation of the
main internal 45.056 MHz DSP core clock from an external 4.096 MHz primary clock or crystal using a x11
multiplication factor. The PLL circuit also includes a by-pass control pin to allow the direct use of an external 2X
(90.102 MHz) clock source applied to the XIN pin.
If the PLL is enabled, the CT8022 primary 45.056 MHz clock can be provided either by attaching a 4.096 MHz
crystal at XIN/XOUT, or by providing a 4.096 MHz clock input at XIN from an external oscillator. Operation of the
PLL is independent of the nature of the primary clock source. If the PLL is disabled, then the clock must be
provided by an external 90.102 MHz clock applied at XIN. The XIN-XOUT internal oscillator is not capable of
supporting operation with an 90.102 MHz crystal.
Operation of the CT8022 at precisely 45.056 MIPS is needed only if the CT8022 is required to generate CODEC
SCLK (master mode) at 2.048 MHz and FSYNC at 8.000 KHz (45.056 MHz = 22 * 2.048 MHz). Selection of the
operating frequency of the CT8022 is affected by the desired modes of operation and the desired sample rates.
45.056 MHz is the maximum operating frequency of the CT8022. If concurrent operation of the AEC is not
required, the operating frequency may be reduced in order to reduce power consumption.
3.25
Power Save Modes
The CT8022 supports internal clock slow-down modes where the clock rate to the internal DSP core can be reduced.
Operation in a slow-down mode affects only the clocks to the CT8022 DSP core. The operation of the CODEC and
Host interfaces is not affected by slowing down the DSP core. The CT8022 also has a minimum power mode, where
all internal clocks are stopped. The internal clock scaling feature of the CT8022 enables the Host to adjust the
available MIPS (and power consumption) to provide just sufficient processing power for the mode of operation used.
The CT8022 supports dynamic clock control, and can be programmed to automatically reduce the clock rate during
the idle time between the processing of each speech frame. This enables power to be conserved even when it is not
possible to use a lower base clock speed.
24
DSP GROUP, INC., 3120 SCOTT BOULEVARD CT8022A11AQC FW Revision 0118
SANTA CLARA, CA 95054 PH: 408 986 – 4300 FAX: 408 986 – 4490
All specifications are subject to change without prior notice.
ETC [ ETC ]
