Version: 1.18
PRELIMINARY/CONFIDENTIAL
TrueSpeech® Co-Processor
10.7
DMA Read from Host Receive Data Buffer Access Port (Burst Mode)
HSTCSN
RXDREQ
t5
t6
RXDACKN
HSTRDN
HSTDB7-0
RX Ready
Buffer Address
IRQN
t1
t2
t4
t3
t8
t7
byte 1
byte 2
byte 2N
Parameter
Description
Min
2 ns
Max
t1
RXDACKN hold time after rising
edge of HSTRDN
t2
t3
HSTRDN to data valid delay
(access time)
Recovery time between DMA
accesses
30 ns
2 * MAINCLOCKP
t4
t5
HSTDRN width
RXDACKN setup time before falling
edge of HSTRDN
2 * MAINCLOCKP
5 ns
t6
t7
t8
Final rising edge of HSTRDN to
RXDREQ de-assertion
Final rising edge of HSTRDN to
IRQN de-assertion
Final rising edge of HSTDRN to RX
Ready de-assertion
MAINCLOCKP
MAINCLOCKP
MAINCLOCKP
Notes:
1. t6, t7, t8 may be negative.
CT8022A11AQC FW Revision 0118 DSP GROUP, INC., 3120 SCOTT BOULEVARD
SANTA CLARA, CA 95054 PH: 408 986 – 4300 FAX: 408 986 – 4490
167
All specifications are subject to change without prior notice.
ETC [ ETC ]
