Version: 1.18
PRELIMINARY/CONFIDENTIAL
TrueSpeech® Co-Processor
11 CT8022 CODEC Interface Timing and AC Specification
11.1
Short Frame Sync
t1
SCLK
1
2
3
4
5
6
7
8
t2
FSYNC
t8
t3
DR0,DR1
DX0,DX1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
t5
t6
Bit 7
t4
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
t7
Parameter
Description
Min
Max
t1
Output delay from rising edge of
SCLK to rising edge of FSYNC
(master mode only)
0 ns
50 ns
t2
t3
FSYNC setup time before falling
edge of SCLK (slave mode only)
FSYNC hold time after falling edge
of SCLK.
50 ns
100 ns
(slave mode only)
t4
t5
t6
t7
SCLK rising edge to data output
valid
data in setup prior to falling edge of
SCLK
data in hold time after falling edge
of SCLK
data out tri-state after final falling
edge of SCLK
0 ns
30 ns
30 ns
30 ns
0.25 * SCLKPERIOD
(122 ns at 2.048 MHz)
0.5 * SCLKPERIOD
(244 ns at 2.048 MHz)
1 SCLK period (nominal)
t8
FSYNC width
(master mode only)
SCLK duty cycle
45%
55%
Notes:
1. SCLK is 2.048 MHz nominal; SCLKPERIOD is 488 ns nominal.
2. Timing diagram shows 8-bit mode only. In 16-bit mode, 16 bits of transmit data are shifted into and out
of the CT8022. Bit 15 occurs first.
CT8022A11AQC FW Revision 0118 DSP GROUP, INC., 3120 SCOTT BOULEVARD
SANTA CLARA, CA 95054 PH: 408 986 – 4300 FAX: 408 986 – 4490
169
All specifications are subject to change without prior notice.
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