TrueSpeech® Co-Processor
PRELIMINARY/CONFIDENTIAL
Version: 1.18
11.2
Long Frame Sync
t1
t3
SCLK
1
2
3
4
5
6
7
8
t2
FSYNC
t8
Bit 5
DR0,DR1
DX0,DX1
Bit 7
Bit 6
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
t9
t5
t6
7
Bit 6
t4
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
t7
Parameter
Description
Min
Max
t1
Output delay from rising edge of
SCLK to rising edge of FSYNC
(master mode only)
0 ns
50 ns
t2
t3
FSYNC setup time before falling
edge of SCLK (slave mode only)
FSYNC hold time after falling edge 100 ns
of SCLK.
50 ns
(slave mode only)
t4
t5
t6
t7
SCLK rising edge to data output
valid
data in setup prior to falling edge of 30 ns
SCLK
data in hold time after falling edge
of SCLK
data out tri-state after final falling
edge of SCLK
0 ns
30 ns
30 ns
0.25 * SCLKPERIOD
(122 ns at 2.048 MHz)
1 SCLK period
0.5 * SCLKPERIOD
(244 ns at 2.048 MHz)
8 SCLK periods in 8-bit
mode (nominal).
16 SCLK periods in 16-
bit mode (nominal).
t8
FSYNC width
master mode
slave mode
t9
ms data bit valid from rising edge of 0 ns
FSYNC. (slave mode only - output
enable delay from FSYNC)
30 ns
SCLK duty cycle
45%
55%
170
DSP GROUP, INC., 3120 SCOTT BOULEVARD CT8022A11AQC FW Revision 0118
SANTA CLARA, CA 95054 PH: 408 986 – 4300 FAX: 408 986 – 4490
All specifications are subject to change without prior notice.
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