Version: 1.18
Notes:
PRELIMINARY/CONFIDENTIAL
TrueSpeech® Co-Processor
1. SLCK is nominally 2.048 MHz.
2. Timing diagram shows 8-bit mode only. In 16-bit mode, 16 bits of data are shifted out of, or into the
CT8022. Bit 15 is shifted first.
3. In master mode, FSYNC is 8 SCLK wide (8-bit mode) or 16 SCLK wide (16-bit mode).
4. In slave mode, FSYNC acts as an output enable for DX0,DX1 for the most signigicant data bit during the
first SCLK period. (There is no internal synchronization delay on the first bit).
5. In slave mode, once the FSYNC signal has been present for one SCLK falling edge, the internal output
enable for DX0 and DX1 is latched and remains active for the appropriate number of SCLK periods.
The DX0 and DX1 outputs remain enabled, regardless of the state of FSYNC until after the final SCLK
falling edge.
6. In master mode, where FSYNC is an output, it may be used as a tri-state control for gating the receive
data. FSYNC will not be de-asserted by the CT8022 until the least significant receive data bit has been
latched internally.
CT8022A11AQC FW Revision 0118 DSP GROUP, INC., 3120 SCOTT BOULEVARD
SANTA CLARA, CA 95054 PH: 408 986 – 4300 FAX: 408 986 – 4490
171
All specifications are subject to change without prior notice.
ETC [ ETC ]
