TrueSpeech® Co-Processor
Notes:
PRELIMINARY/CONFIDENTIAL
Version: 1.18
1. Internal Buffer Address cleared by transition of RX Ready bit from 0 to 1.
2. Internal Buffer Address increments on HSTRDN only if HSTAB0 = 1.
3. RX Ready bit clears on final HSTRDN after N accesses with HSTAB0=1, where N is the Frame Size value
(word count).
4. RXDREQ asserted if DMA enable bit is set in the Hardware Control Register.
5. RXDREQ may operate in Burst Mode or Single Cycle Mode.
6. IRQN driven by RX Ready if RX Ready IE bit is set in the Host Hardware Control Register.
7. t7, t8, t9 may be negative.
164
DSP GROUP, INC., 3120 SCOTT BOULEVARD CT8022A11AQC FW Revision 0118
SANTA CLARA, CA 95054 PH: 408 986 – 4300 FAX: 408 986 – 4490
All specifications are subject to change without prior notice.
ETC [ ETC ]
