TrueSpeech® Co-Processor
PRELIMINARY/CONFIDENTIAL
Version: 1.18
10.6
DMA Write to Host Transmit Data Buffer Access Port (Single Cycle Mode)
HSTCSN
t1
t2
TXDREQ
TXDACKN
HSTWRN
HSTDB7-0
TX Ready
Buffer Address
IRQN
t4
t3
byte 1
byte 2
byte 2N
Parameter
Description
Min
Max
t1
TXDACKN asserted to TXDREQ
de-asserted response time
3 * MAINCLOCKP
t2
t3
TXDREQ re-assertion delay
TXDACKN setup time before falling
edge of HSTWRN
16 * MAINCLOCKP
5 ns
t4
TXDACKN hold time after rising
edge of HSTWRN
2 ns
166
DSP GROUP, INC., 3120 SCOTT BOULEVARD CT8022A11AQC FW Revision 0118
SANTA CLARA, CA 95054 PH: 408 986 – 4300 FAX: 408 986 – 4490
All specifications are subject to change without prior notice.
ETC [ ETC ]
