Version: 1.18
PRELIMINARY/CONFIDENTIAL
TrueSpeech® Co-Processor
10.5
DMA Write to Host Transmit Data Buffer Access Port (Burst Mode)
HSTCSN
t5
TXDREQ
TXDACKN
HSTWRN
HSTDB7-0
TX Ready
Buffer Address
IRQN
t8
t9
t3
t1
t2
t4
t6
t7
byte 2N
byte 1
byte 2
Parameter
Description
HSTWRN width
Recovery time between Host
accesses
Min
Max
t1
t2
2 * MAINCLOCKP
2 * MAINCLOCKP
t3
t4
t5
t6
t7
t8
t9
HSTDB7-0 setup time before rising
edge of HSTWRN
HSTDB7-0 hold time after rising
edge of HSTWRN
TXDREQ de-asserted after final
rising edge of HSTWRN
Final rising edge of HSTWRN to TX
Ready cleared
Final rising edge of HSTWRN to
IRQN cleared
TXDACKN asserted before
HSTWRN
TXDACKN hold time after rising
edge of HSTWRN
20 ns
5 ns
MAINCLOCKP
MAINCLOCKP
MAINCLOCKP
5 ns
2 ns
Notes:
1. t5, t6, t7 may be negative.
CT8022A11AQC FW Revision 0118 DSP GROUP, INC., 3120 SCOTT BOULEVARD
SANTA CLARA, CA 95054 PH: 408 986 – 4300 FAX: 408 986 – 4490
165
All specifications are subject to change without prior notice.
ETC [ ETC ]
