TrueSpeech® Co-Processor
PRELIMINARY/CONFIDENTIAL
Version: 1.18
10.3
Host Write to Host Transmit Data Buffer Access Port
t2
t7
HSTWRN
t9
HSTCSN
t3
HSTAB0
HSTA3-1
t1
t4
HSTDB7-0
TX Ready
TXDREQ
t5
t8
t6
Buffer Address
IRQN
byte 1
byte 2
byte 2N
Parameter
Description
Min
Max
t1
HSTAB0-3 hold time after rising
edge of HSTWRN or HSTCSN
2 ns
t2
t3
t4
t5
t6
Recovery time between Host
accesses
HSTDB7-0 setup time before rising
edge of HSTWRN or HSTCSN
HSTDB7-0 hold time after rising
edge of HSTWRN or HSTCSN
Final rising edge of HSTWRN to TX
Ready cleared
2 * MAINCLOCKP
20 ns
5 ns
MAINCLOCKP
MAINCLOCKP
Final rising edge of HSTWRN to
TXDREQ cleared
t7
t8
HSTWRN width
Final rising edge of HSTWRN to
IRQN de-asserted
HSTAB3-0 valid before HSTWRN
asserted
2 * MAINCLOCKP
5 ns
MAINCLOCKP
t9
Notes:
1. Internal Buffer Address cleared by transition of TX Ready bit from 0 to 1.
2. Internal Buffer Address increments on rising edge of HSTWRN only if HSTAB0 = 1.
3. TX Ready bit clears on final HSTWRN after N access with HSTAB0 =1, where N is the Frame Size value
(word count).
4. TXDREQ asserted if TX DMA Enable bit is set in the Hardware Control Register.
5. TXDREQ may operate in Burst Mode or Single Cycle Mode.
6. IRQN driven by TX Ready if TX Ready IE bit set in Host Hardware Control Register.
7. t5, t6 and t8 may be negative.
162
DSP GROUP, INC., 3120 SCOTT BOULEVARD CT8022A11AQC FW Revision 0118
SANTA CLARA, CA 95054 PH: 408 986 – 4300 FAX: 408 986 – 4490
All specifications are subject to change without prior notice.
ETC [ ETC ]
