Version: 1.18
PRELIMINARY/CONFIDENTIAL
TrueSpeech® Co-Processor
10.2
Host Read from Software Status Register Most Significant Byte
t5
HSTRDN
t7
t1
HSTCSN
HSTAB0
t2
t6
HSTAB3-1
HSTDB7-0
t3
IRQN
Status Ready
t4
Parameter
Description
Min
Max
t1
t2
t3
HSTRDN or HSTCSN to data out
valid
HSTAB3-0 setup time before falling
edge of HSTRDN or HSTCSN
HSTRDN or HSTCSN inactive to
data out tri-state (output disable
delay)
30 ns
5 ns
30 ns
t4
HSTRDN or HSTCSN positive
edge to Status Ready clear
MAINCLOCKP
t5
t6
HSTRDN or HSTCSN width
HSTAB3-0 hold time after positive
edge of HSTRDN or HSTCSN
2 * MAINCLOCKP
2 ns
t7
Recovery time between Host
Accesses
2 * MAINCLOCKP
Notes:
1. Internal DSP write to Software Status Register (or Aux Software Status Register) sets Status Ready bit in
Host Hardware Status Register.
2. IRQN asserted to Host assumes that the appropriate IE bit is set in the Host Hardware Control Register.
3. Host read of Software Status Register most significant byte clears Status Ready bit, de-asserts IRQN.
The Status Ready bit illustrated is the bit that is visible to the Host in the Hardware Status Register.
4. t4 may be negative.
CT8022A11AQC FW Revision 0118 DSP GROUP, INC., 3120 SCOTT BOULEVARD
SANTA CLARA, CA 95054 PH: 408 986 – 4300 FAX: 408 986 – 4490
161
All specifications are subject to change without prior notice.
ETC [ ETC ]
