TrueSpeech® Co-Processor
PRELIMINARY/CONFIDENTIAL
Version: 1.18
10 CT8022 Host Interface Timing
10.1
Host Write to Software Control Register Most Significant Byte
t1
t5
HSTWRN
HSTAB0
t2
t3
sw control reg address
HSTAB3-1
HSTDB7-0
HSTCSN
t7
t6
Control Ready
t4
Parameter
Description
Min
Max
t1
t2
HSTWRN pulse width
HSTAB3-0 setup time before falling
edge of HSTWRN or HSTCSN
2 * MAINCLOCKP
5 ns
t3
t4
HSTAB3-0 hold time after rising
edge of HSTWRN or HSTCSN
Delay from rising edge of HSTWRN
or HSTCSN to Control Ready
cleared
2 ns
MAINCLOCKP
t5
t6
t7
Recovery time between Host
accesses
HSTDB7-0 setup time before rising
edge of HSTWRN or HSTCSN
HSTDB7-0 hold time after rising
edge of HSTWRN or HSTCSN
2 * MAINCLOCKP
20 ns
5 ns
Notes:
1. Host writes to most significant byte of Software Control Register.
2. Same timings apply to writes to Aux Control Register.
3. Control Ready (or Aux Control Ready) cleared by Host Write to Software Control Register (or Aux
Software Control Register). Control Ready bit visible to Host in Hardware Status Register. Must be
valid in time for read by next Host access.
4. MAINCLOCKP period = 2/XIN (effective) = 22.2 ns at 45.056 Mips with 4.096 MHz external crystal or
90.112 MHz external clock.
5. t4 may be negative.
6. t4 must be less than t5 so that Control Ready is valid for the next Host access. The Control Ready signal
illustrated is the bit visible to the Host in the Hardware Status Register.
160
DSP GROUP, INC., 3120 SCOTT BOULEVARD CT8022A11AQC FW Revision 0118
SANTA CLARA, CA 95054 PH: 408 986 – 4300 FAX: 408 986 – 4490
All specifications are subject to change without prior notice.
ETC [ ETC ]
