R
XC5200 Series Field Programmable Gate Arrays
XC5200 CLB Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used
in the simulator.
Speed Grade
Symbol
-6
-5
-4
-3
Min
(ns)
Max
(ns)
Min
(ns)
Max
(ns)
Min
(ns)
Max
(ns)
Min
(ns)
Max
(ns)
Description
Combinatorial Delays
F inputs to X output
TILO
TITO
TIDO
5.6
8.0
4.3
4.6
6.6
3.5
3.8
5.4
2.8
3.0
4.3
2.4
F inputs via transparent latch to Q
DI inputs to DO output (Logic-Cell
Feedthrough)
F inputs via F5_MUX to DO output
Carry Delays
TIMO
7.2
5.8
5.0
4.3
Incremental delay per bit
Carry-in overhead from DI
Carry-in overhead from F
Carry-out overhead to DO
Sequential Delays
TCY
TCYDI
TCYL
TCYO
0.7
1.8
3.7
4.0
0.6
1.6
3.2
3.2
0.5
1.5
2.9
2.5
0.5
1.4
2.4
2.1
Clock (CK) to out (Q) (Flip-Flop)
TCKO
5.8
9.2
4.9
7.4
4.0
5.9
4.0
5.5
Gate (Latch enable) going active to out (Q)
Set-up Time Before Clock (CK)
F inputs
TGO
7
TICK
TMICK
TDICK
TEICK
2.3
3.8
0.8
1.6
1.8
3.0
0.5
1.2
1.4
2.5
0.4
0.9
1.3
2.4
0.4
0.9
F inputs via F5_MUX
DI input
CE input
Hold Times After Clock (CK)
F inputs
TCKI
TCKMI
TCKDI
TCKEI
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F inputs via F5_MUX
DI input
CE input
Clock Widths
Clock High Time
TCH
TCL
6.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0
Clock Low Time
Toggle Frequency (MHz) (Note 3)
Reset Delays
FTOG
83
83
83
83
Width (High)
TCLRW
TCLR
6.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0
Delay from CLR to Q (Flip-Flop)
Delay from CLR to Q (Latch)
Global Reset Delays
Width (High)
7.7
6.5
6.3
5.2
5.1
4.2
4.0
3.0
TCLRL
TGCLRW
TGCLR
Delay from internal GR to Q
14.7
12.1
9.1
8.0
Note: 1. The CLB K to Q output delay (T
CKO
) of any CLB, plus the shortest possible interconnect delay, is always longer than the
) of any CLB on the same die.
Data In hold-time requirement (T
CKDI
2. Timing is based upon the XC5215 device. For other devices, see Timing Calculator.
3. Maximum flip-flop toggle rate for export control purposes.
November 5, 1998 (Version 5.2)
7-129
ETC [ ETC ]
