R
XC5200 Series Field Programmable Gate Arrays
XC5200 Guaranteed Input and Output Parameters (Pin-to-Pin)
All values listed below are tested directly, and guaranteed over the operating conditions. The same parameters can also be
derived indirectly from the Global Buffer specifications. The delay calculator uses this indirect method, and may
overestimate because of worst-case assumptions. When there is a discrepancy between these two methods, the values
listed below should be used, and the derived values should be considered conservative overestimates.
Speed Grade
-6
-5
-4
-3
Max
(ns)
Max
(ns)
Max
(ns)
Max
(ns)
Description
Symbol Device
Global Clock to Output Pad (fast)
TICKOF
(Max)
XC5202
XC5204
XC5206
XC5210
XC5215
XC5202
XC5204
XC5206
XC5210
XC5215
XC5202
XC5204
XC5206
XC5210
XC5215
XC5202
XC5204
XC5206
XC5210
XC5215
XC5202
XC5204
XC5206
XC5210
XC5215
XC5202
XC5204
XC5206
XC5210
XC5215
XC52xx
16.9
17.1
17.2
17.2
19.0
21.4
21.6
21.7
21.7
24.3
2.5
15.1
15.3
15.4
15.4
17.0
18.7
18.9
19.0
19.0
21.2
2.0
10.9
11.3
11.9
12.8
12.8
12.6
13.3
13.6
15.0
15.0
1.9
9.8
9.9
10.8
11.2
11.7
11.5
11.9
12.5
12.9
13.1
1.9
1.9
1.9
1.8
1.7
3.5
3.6
4.3
4.8
5.6
6.6
6.6
6.3
6.0
5.7
7.5
7.5
7.4
7.3
7.2
0
CLB
Q
Direct IOB
Connect
BUFG
.
.
.
.
FAST
Global Clock-to-Output Delay
Global Clock to Output Pad (slew-limited)
TICKO
CLB
Q
Direct IOB
Connect
(Max)
BUFG
.
.
.
.
Global Clock-to-Output Delay
Input Set-up Time (no delay) to CLB Flip-Flop
TPSUF
(Min)
Direct
IOB(NODELAY)
CLB
F,DI
2.3
1.9
1.9
Connect
Input
Set-up
& Hold
Time
2.2
1.9
1.9
2.2
1.9
1.9
BUFG
2.0
1.8
1.7
Input Hold Time (no delay) to CLB Flip-Flop
TPHF
3.8
3.8
3.5
Direct
IOB(NODELAY)
CLB
3.9
3.9
3.8
Connect
Input
(Min)
F,DI
4.4
4.4
4.4
Set-up
& Hold
Time
5.1
5.1
4.9
BUFG
5.8
5.8
5.7
Input Set-up Time (with delay) to CLB Flip-Flop DI Input
TPSU
7.3
6.6
6.6
Direct
IOB
CLB
DI
7.3
6.6
6.6
Connect
Input
Set-up
& Hold
Time
7.2
6.5
6.4
7.2
6.5
6.0
BUFG
6.8
5.7
5.7
Input Set-up Time (with delay) to CLB Flip-Flop F Input
TPSUL
(Min)
8.8
7.7
7.5
Direct
IOB
CLB
F
8.6
7.5
7.5
Connect
Input
Set-up
& Hold
Time
8.5
7.4
7.4
8.5
7.4
7.4
BUFG
8.5
7.4
7.4
Input Hold Time (with delay) to CLB Flip-Flop
TPH
0
0
0
Direct
IOB
CLB
F,DI
Connect
Input
Set-up
& Hold
Time
(Min)
BUFG
Note: 1. These measurements assume that the CLB flip-flop uses a direct interconnect to or from the IOB. The INREG/ OUTREG
properties, or XACT-Performance, can be used to assure that direct connects are used. tPSU applies only to the CLB input
DI that bypasses the look-up table, which only offers direct connects to IOBs on the left and right edges of the die. tPSUL
applies to the CLB inputs F that feed the look-up table, which offers direct connect to IOBs on all four edges, as do the CLB
Q outputs.
2. When testing outputs (fast or slew-limited), half of the outputs on one side of the device are switching.
7-130
November 5, 1998 (Version 5.2)
ETC [ ETC ]
