R
XC5200 Series Field Programmable Gate Arrays
XC5200 Boundary Scan (JTAG) Switching Characteristic Guidelines
The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units
of nanoseconds and apply to all XC5200 devices unless otherwise noted.
Speed Grade
Symbol
-6
-5
-4
-3
Description
Setup and Hold
Min
Max
Min
Max
Min
Max
Min
Max
Input (TDI) to clock (TCK)
setup time
Input (TDI) to clock (TCK)
hold time
T
T
30.0
0
30.0
0
30.0
0
30.0
0
TDITCK
TCKTDI
Input (TMS) to clock (TCK)
setup time
Input (TMS) to clock (TCK)
hold time
T
T
15.0
0
15.0
0
15.0
0
15.0
0
TMSTCK
TCKTMS
Propagation Delay
Clock (TCK) to Pad (TDO)
T
30.0
10.0
30.0
10.0
30.0
10.0
30.0
10.0
TCKPO
Clock
Clock (TCK) High
Clock (TCK) Low
T
T
30.0
30.0
30.0
30.0
30.0
30.0
30.0
30.0
TCKH
TCKL
F
(MHz)
F
MAX
MAX
Note 1:
Input pad setup and hold times are specified with respect to the internal clock.
7-132
November 5, 1998 (Version 5.2)
ETC [ ETC ]
