R
XC5200 Series Field Programmable Gate Arrays
Configuration Switching Characteristics
T
Vcc
PROGRAM
INIT
POR
RE-PROGRAM
>300 ns
T
PI
T
T
ICCK
CCLK
CCLK OUTPUT or INPUT
<300 ns
<300 ns
M0, M1, M2
(Required)
DONE RESPONSE
I/O
VALID
X1532
Master Modes
Description
Symbol
Min
Max
Units
Power-On-Reset
Program Latency
CCLK (output) Delay
period (slow)
T
2
15
70
ms
POR
T
6
µs per CLB column
PI
T
40
640
100
375
3000
375
µs
ns
ns
7
ICCK
CCLK
CCLK
T
T
period (fast)
Slave and Peripheral Modes
Description
Power-On-Reset
Symbol
Min
2
Max
15
Units
ms
T
POR
Program Latency
T
6
70
µs per CLB column
PI
CCLK (input) Delay (required)
period (required)
T
5
100
µs
ns
ICCK
T
CCLK
Note:
At power-up, VCC must rise from 2.0 to VCC min in less than 15 ms, otherwise delay configuration using PROGRAM until
VCC is valid.
November 5, 1998 (Version 5.2)
7-125
ETC [ ETC ]
