R
XC5200 Series Field Programmable Gate Arrays
Device-Specific Pinout Tables
Device-specific tables include all packages for each XC5200-Series device. They follow the pad locations around the die,
and include boundary scan register locations.
Pin Locations for XC5202 Devices
The following table may contain pinout information for unsupported device/package combinations. Please see the
availability charts elsewhere in the XC5200 Series data sheet for availability information.
Pin
Description
VQ64*
PC84
PQ100
VQ100
TQ144
PG156
Boundary Scan Order
VCC
-
57
58
-
2
3
92
93
94
95
96
97
98
-
89
90
91
92
93
94
95
-
128
129
130
131
132
133
134
137
138
139
142
143
144
1
H3
H1
-
1.
2.
3.
4.
5.
6.
I/O (A8)
I/O (A9)
I/O
51
4
G1
G2
G3
F1
54
-
57
I/O
-
-
63
I/O (A10)
I/O (A11)
GND
-
5
66
59
-
6
F2
69
-
F3
-
7.
I/O (A12)
I/O (A13)
I/O (A14)
I/O (A15)
VCC
60
61
62
63
64
-
7
99
100
1
96
97
98
99
100
1
E3
78
8.
8
C1
81
9.
9
B1
90
10.
10
11
12
13
14
15
16
-
2
B2
93
3
C3
-
GND
4
C4
-
11.
12.
13.
14.
GCK1 (A16, I/O)
I/O (A17)
I/O (TDI)
I/O (TCK)
GND
1
5
2
2
B3
102
105
111
114
-
2
6
3
3
A1
7
3
7
4
6
B4
4
8
5
7
A3
-
-
-
8
C6
15.
16.
17.
18.
19.
20.
I/O (TMS)
I/O
5
17
18
-
9
6
11
12
13
14
15
16
17
18
19
20
21
22
23
24
27
28
29
32
33
34
35
36
37
38
39
A5
117
123
126
129
135
138
-
6
10
-
7
C7
I/O
-
-
B7
I/O
-
-
11
12
13
14
15
16
17
18
-
8
A6
I/O
-
19
20
21
22
23
24
-
9
A7
I/O
7
10
11
12
13
14
15
-
A8
GND
8
C8
VCC
9
B8
-
21.
22.
23.
24.
25.
26.
I/O
-
C9
141
147
150
153
159
162
-
I/O
10
B9
I/O
A9
I/O
-
B10
C10
A10
C11
B12
A13
B13
B14
A15
C13
A16
C14
B15
B16
I/O
-
25
26
-
19
20
-
16
17
-
I/O
11
GND
27.
28.
29.
30.
31.
I/O
12
27
-
21
22
23
24
25
26
27
28
29
30
18
19
20
21
22
23
24
25
26
27
165
171
174
177
186
-
I/O
I/O
13
14
15
-
28
29
30
31
32
33
34
35
I/O
M1 (I/O)
GND
32.
M0 (I/O)
VCC
16
-
189
-
33.
34.
M2 (I/O)
GCK2 (I/O)
17
18
192
195
November 5, 1998 (Version 5.2)
7-133
ETC [ ETC ]
