July 2004
AS91L1006BU
PIN
PIN
PIN
TYPE
Stable state
after port/reset
PIN NAME
NUMBER NUMBER
LQFP
DESCRIPTION
FPBGA
LSP6_TCK
LSP6_TMS
LSP6_TDO
OUT
OUT
OUT
61
F10
IEEE1149.1 Test Clock on LSP 6
when PASS_THRU_ENABLE is
HIGH.
Buffered version
of signal present
on primary TCK
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 101.
This pin is tri-stated for all other
combinations.
IEEE1149.1 Test Mode Select on
LSP 6 when PASS_THRU_ENABLE
is HIGH.
60
F9
Logic '1'
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 101.
This pin is tri-stated for all other
combinations.
IEEE1149.1 Test Data Out on LSP 6 Logic '1'
when PASS_THRU_ENABLE is
HIGH.
57
G10
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 101.
This pin is tri-stated for all other
combinations.
LSP6_TDI
IN
58
64
G8
E9
IEEE1149.1 Test Data In on LSP 6
when PASS_THRU_ENABLE is
HIGH.
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 101.
IEEE1149.1 Test Reset on LSP 5
when PASS_THRU_ENABLE is
HIGH.
LSP6_TRST
OUT
Buffered version
of signal present
on primary TRST
Pin is in Pass-Through mode when
PASS_THRU_ENABLE = 0 and
PASS_THRU_SEL[2:0] = 101.
This pin is tri-stated for all other
combinations.
www.alsc.com
Alliance Semiconductor
2003, 2004 © Copyright Alliance Semiconductor Corporation. All Rights reserved.
17
ETC [ ETC ]
